1127 commits

Author	SHA1	Message	Date
Eddie Hung	4d6fac019a	Fix spacing	2019-06-21 16:06:13 -07:00
Eddie Hung	aa0b107afb	synth_xilinx to use _ABC macro, and perform muxpack again	2019-06-21 15:48:20 -07:00
Eddie Hung	9abde12110	Add $__XILINX_MUXF78 to preserve entire box	2019-06-21 15:47:42 -07:00
Eddie Hung	7acbea6b28	Fix alignment	2019-06-21 14:38:30 -07:00
Eddie Hung	f433a52374	Add FIXME about need for -mux4	2019-06-21 11:15:23 -07:00
Eddie Hung	c6b4653ebe	Since muxcover uses MUX4s, blast them back to gates here	2019-06-21 11:13:01 -07:00
Eddie Hung	dd22edcd28	Expand synth -coarse without wreduce, move muxcover	2019-06-21 11:12:32 -07:00
David Shah	a0d3d2bb41	ecp5: Improve mapping of $alu when BI is used ... Signed-off-by: David Shah <dave@ds0.me>	2019-06-21 09:45:11 +01:00
Eddie Hung	e612dade12	Merge remote-tracking branch 'origin/master' into xaig	2019-06-20 19:00:36 -07:00
Eddie Hung	f11c9a419b	Call opt_expr -mux_undef to get rid of 1'bx in muxes prior to abc	2019-06-20 17:38:16 -07:00
Eddie Hung	d1dadfcec8	Call opt_expr -mux_undef to get rid of 1'bx in muxes prior to abc	2019-06-20 16:45:09 -07:00
Eddie Hung	9faab38e8d	mux_map to drop sign bit, and eliminate 'bx-es	2019-06-20 16:45:04 -07:00
Eddie Hung	f374e0ab7e	Merge remote-tracking branch 'origin/master' into xc7mux	2019-06-20 10:18:01 -07:00
acw1251	ce29ede801	Fixed small typo in ice40_unlut help summary	2019-06-19 16:39:46 -04:00
acw1251	0d888ee7ed	Fixed the help summary line for a few commands	2019-06-19 15:27:04 -04:00
Eddie Hung	4ca847a217	Merge remote-tracking branch 'origin/xaig' into xc7mux	2019-06-18 11:49:54 -07:00
Eddie Hung	8e0a47fb92	Really permute Xilinx LUT mappings as default LUT6.I5:A6	2019-06-18 11:48:48 -07:00
Eddie Hung	8f5e6d73ff	Revert "Fix (do not) permute LUT inputs, but permute mux selects" ... This reverts commit da3d2eedd2.	2019-06-18 11:35:21 -07:00
Eddie Hung	3d283e69f8	Merge remote-tracking branch 'origin/xaig' into xc7mux	2019-06-18 09:51:28 -07:00
Eddie Hung	b304744d15	Clean up	2019-06-18 09:50:37 -07:00
Eddie Hung	da3d2eedd2	Fix (do not) permute LUT inputs, but permute mux selects	2019-06-18 09:49:57 -07:00
Eddie Hung	2b0e28b261	Merge remote-tracking branch 'origin/xaig' into xc7mux	2019-06-17 22:29:34 -07:00
Eddie Hung	608a95eb01	Fix copy-pasta issue	2019-06-17 22:29:22 -07:00
Eddie Hung	59b4e69d16	Merge remote-tracking branch 'origin/xaig' into xc7mux	2019-06-17 22:25:14 -07:00
Eddie Hung	2a35c4ef94	Permute INIT for +/xilinx/lut_map.v	2019-06-17 22:24:35 -07:00
Eddie Hung	75f8b4cf10	Simplify comment	2019-06-17 19:14:41 -07:00
Eddie Hung	9d56c0d525	Merge remote-tracking branch 'origin/xaig' into xc7mux	2019-06-17 18:25:35 -07:00
Eddie Hung	840562943f	Update LUT7/8 delays to take account for [ABC]OUTMUX delay	2019-06-17 17:06:01 -07:00
Eddie Hung	c15ee827f4	Try -W 300	2019-06-17 10:29:06 -07:00
Eddie Hung	1ec450d6bf	Try -W 300	2019-06-16 12:08:03 -07:00
Eddie Hung	842c110357	Merge remote-tracking branch 'origin/xaig' into xc7mux	2019-06-15 05:48:47 -07:00
Eddie Hung	bf312043d4	Fix upper XC7 LUT[78] delays to use I[01] -> O delay not S -> O	2019-06-15 05:45:16 -07:00
Eddie Hung	b63b2a0bd4	Revert "Remove wide mux inference" ... This reverts commit 738fdfe8f5.	2019-06-14 12:50:24 -07:00
Eddie Hung	8fa74287a7	As per @daveshah1 remove async DFF timing from xilinx	2019-06-14 12:43:20 -07:00
Eddie Hung	97d2656375	Resolve comments from @daveshah1	2019-06-14 12:00:02 -07:00
Eddie Hung	2e34859a6b	Add XC7_WIRE_DELAY macro to synth_xilinx.cc	2019-06-14 11:38:22 -07:00
Eddie Hung	ba4b4a0088	Update delays based on SymbiFlow/prjxray-db	2019-06-14 11:33:10 -07:00
Eddie Hung	d47ff7ba87	Rename +/xilinx/abc.{box,lut} -> abc_xc7.{box,lut}	2019-06-14 10:51:11 -07:00
Eddie Hung	94314ae2d5	Comment out dist RAM boxing on ECP5 for now	2019-06-14 10:42:30 -07:00
Eddie Hung	ee428f73ab	Remove WIP ABC9 flop support	2019-06-14 10:37:52 -07:00
Eddie Hung	627a62a797	Make doc consistent	2019-06-14 10:32:46 -07:00
David Shah	9566573054	ecp5: Add abc9 option ... Signed-off-by: David Shah <dave@ds0.me>	2019-06-14 17:15:02 +01:00
Eddie Hung	75d89e56cf	Fix name clash	2019-06-13 14:27:07 -07:00
Eddie Hung	2052806d33	Fix LP SB_LUT4 timing	2019-06-13 08:24:33 -07:00
Eddie Hung	009255d11d	Move neg-pol to pos-pol mapping from ff_map to cells_map.v	2019-06-12 16:07:24 -07:00
Eddie Hung	c7f5091c2f	Reduce diff with master	2019-06-12 09:34:41 -07:00
Eddie Hung	f9433cc34b	Remove abc_flop{,_d} attributes from ice40/cells_sim.v	2019-06-12 09:29:30 -07:00
Eddie Hung	99267f660f	Fix spacing	2019-06-12 09:21:52 -07:00
Eddie Hung	738fdfe8f5	Remove wide mux inference	2019-06-12 09:20:46 -07:00
Eddie Hung	1e838a8913	Retry "Add "-W' wire delay arg to abc9, use from synth_xilinx"	2019-06-12 08:49:15 -07:00