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Author	SHA1	Message	Date
Clifford Wolf	d267bcde4e	Fixed bug in sequential sat proofs and improved handling of asserts	2014-02-04 12:46:16 +01:00
Clifford Wolf	ecdf1f5577	Improved handling of reg init in opt_share and opt_rmdff	2014-02-04 12:02:47 +01:00
Clifford Wolf	9e938aa32a	presentation progress	2014-02-04 00:57:11 +01:00
Clifford Wolf	6c3d767976	presentation progress	2014-02-03 16:26:27 +01:00
Clifford Wolf	9e35021585	Addred sat option -ignore_unknown_cells	2014-02-03 16:26:10 +01:00
Clifford Wolf	a6750b3753	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	2014-02-03 13:01:45 +01:00
Clifford Wolf	de9226a64f	Replaced isim with xsim in tests/tools/autotest.sh, removed xst support	2014-02-03 13:00:55 +01:00
Clifford Wolf	de336d93b2	More opt_const -mux_bool features	2014-02-02 22:41:24 +01:00
Clifford Wolf	982c9da011	presentation progress	2014-02-02 22:26:26 +01:00
Clifford Wolf	9d0b69edaa	Added opt_const -mux_bool	2014-02-02 22:11:08 +01:00
Clifford Wolf	bee4450c4c	Added support for inverter chains to opt_const	2014-02-02 21:46:42 +01:00
Clifford Wolf	f9c4d33909	Added RTLIL::SigSpec::to_single_sigbit()	2014-02-02 21:35:26 +01:00
Clifford Wolf	67b0ce2578	Only generate write-enable $and if WE is not constant 1 in memory_map	2014-02-02 21:27:26 +01:00
Clifford Wolf	83fa652820	Added constant-clock case to opt_rmdff	2014-02-02 21:09:08 +01:00
Clifford Wolf	6983d3f10b	presentation progress	2014-02-02 17:57:14 +01:00
Clifford Wolf	aa732b0c73	Added show -notitle option	2014-02-02 17:55:32 +01:00
Clifford Wolf	9808acdc75	Added delete command	2014-02-02 17:11:19 +01:00
Clifford Wolf	a9e2d86f86	Added suuport for module attribute matching with A:<pattern>[=<pattern>] syntax	2014-02-02 16:47:17 +01:00
Clifford Wolf	0f88e28693	presentation progress	2014-02-02 13:30:49 +01:00
Clifford Wolf	9334c34170	presentation progress	2014-02-02 13:06:28 +01:00
Clifford Wolf	cdd6e11af5	Added support for blanks after -I and -D in read_verilog	2014-02-02 13:06:21 +01:00
Clifford Wolf	f4f0bd6eef	Fixed a bug in miter command	2014-02-01 22:53:27 +01:00
Clifford Wolf	374674aff4	Added sat -show-inputs and -show-outputs	2014-02-01 22:52:44 +01:00
Clifford Wolf	caf540d1ad	Added show -color support for cells and finished show -label implementation	2014-02-01 18:23:32 +01:00
Clifford Wolf	af325bf206	Fixed comment/eol parsing in ilang frontend	2014-02-01 17:28:02 +01:00
Clifford Wolf	d06258f74f	Added constant size expression support of sized constants	2014-02-01 13:50:23 +01:00
Clifford Wolf	1e2440e7ed	Added note about SystemVerilog assert statement to README	2014-02-01 13:04:49 +01:00
Clifford Wolf	fa92722358	Added miter command	2014-02-01 10:35:56 +01:00
Clifford Wolf	1c8f6f21b4	Progress on presentation	2014-01-31 12:48:31 +01:00
Clifford Wolf	ed8ad99960	More changes to techlibs/common/simlib.v for LEC	2014-01-31 11:21:29 +01:00
Clifford Wolf	36a808c572	presentation progress	2014-01-30 15:25:09 +01:00
Clifford Wolf	4df7e03ec9	Bugfix in name resolution with generate blocks	2014-01-30 15:01:28 +01:00
Clifford Wolf	672229eda5	Added yosys -H for command list	2014-01-30 12:32:59 +01:00
Clifford Wolf	34b39ec28a	presentation progress	2014-01-29 15:56:58 +01:00
Clifford Wolf	cbe77bf844	presentation progress	2014-01-29 12:15:38 +01:00
Clifford Wolf	aceab5fc08	Tiny change in example script in README	2014-01-29 11:11:10 +01:00
Clifford Wolf	96084e9864	Added -h command line option	2014-01-29 11:10:39 +01:00
Clifford Wolf	6a7d7e847d	Added test comments to techlibs/cmos/cmos_cells.lib	2014-01-29 10:51:02 +01:00
Clifford Wolf	c46b23ab23	Updated ABC to hg rev e6b09e1	2014-01-29 10:50:15 +01:00
Clifford Wolf	375c4dddc1	Added read_verilog -icells option	2014-01-29 00:59:28 +01:00
Clifford Wolf	a86f33653d	Major rewrite of techlibs/common/simlib.v for LEC (cadance conformal)	2014-01-29 00:36:03 +01:00
Clifford Wolf	961b791272	presentation progress	2014-01-28 20:28:22 +01:00
Clifford Wolf	2cb47355d4	Renamed manual/FILES_* directories	2014-01-28 06:55:47 +01:00
Clifford Wolf	842ca2f011	Progress on presentation	2014-01-28 06:51:50 +01:00
Clifford Wolf	a3ac6b6f47	Progress on presentation	2014-01-27 20:42:35 +01:00
Clifford Wolf	fb4c3dff33	Added first presentation slides	2014-01-27 17:08:19 +01:00
Clifford Wolf	fa103e55ad	Merge branch 'btor' of https://github.com/ahmedirfan1983/yosys	2014-01-26 02:29:19 +01:00
Clifford Wolf	fd6ca84f3c	Merge pull request #21 from hansiglaser/master ... beautified write_intersynth, enabled multiple "-map" for the extract pass	2014-01-25 17:28:17 -08:00
Johann Glaser	e9a2094774	enabled multiple "-map" for the extract pass	2014-01-25 21:11:34 +01:00
Johann Glaser	f13b3518aa	beautified write_intersynth	2014-01-25 20:16:38 +01:00