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Code Activity
8724 commits 122 branches 59 tags 73 MiB
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1189 commits

Author SHA1 Message Date
Eddie Hung
d20c1dac73 verilog: ignore ranges too without -specify 2020-02-13 17:58:43 -08:00
Eddie Hung
6b58c1820c verilog: improve specify support when not in -specify mode 2020-02-13 13:27:15 -08:00
Eddie Hung
2e51dc1856 verilog: ignore '&&&' when not in -specify mode 2020-02-13 13:06:13 -08:00
Eddie Hung
b523ecf2f4 specify: system timing checks to accept min:typ:max triple 2020-02-13 12:42:15 -08:00
Eddie Hung
7cfdf4ffa7 verilog: fix $specify3 check 2020-02-13 12:42:04 -08:00
N. Engelhardt
e069259a53
Merge pull request #1679 from thasti/delay-parsing 
Fix crash on wire declaration with delay
 2020-02-13 12:01:27 +01:00
Rodrigo Alejandro Melo
da485dc007 Modified $readmem[hb] to use '\' or '/' according the OS 
Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
 2020-02-06 10:10:29 -03:00
Stefan Biereigel
b844b078db correct wire declaration grammar for #1614 2020-02-03 21:29:40 +01:00
Rodrigo Alejandro Melo
313a425bd5 Merge branch 'master' of https://github.com/YosysHQ/yosys 
Solved a conflict into the CHANGELOG

Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
 2020-02-03 10:56:41 -03:00
Rodrigo Alejandro Melo
71f3afb9a2 Replaced strlen by GetSize into simplify.cc 
As recommended in CodingReadme.

Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
 2020-02-03 10:44:09 -03:00
David Shah
4bfd2ef4f3 sv: Improve handling of wildcard port connections 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-02 16:12:33 +00:00
David Shah
5df591c023 hierarchy: Resolve SV wildcard port connections 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-02 16:12:33 +00:00
David Shah
50f86c11b2 sv: Add lexing and parsing of .* (wildcard port conns) 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-02 16:12:33 +00:00
David Shah
9f5613100b
Merge pull request #1647 from YosysHQ/dave/sprintf 
ast: Add support for $sformatf system function
 2020-02-02 14:53:46 +00:00
Rodrigo Alejandro Melo
b4c30cfc8d Fixed a bug in the new feature of $readmem[hb] when an empty string is provided 
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
 2020-02-01 17:03:56 -03:00
Rodrigo Alejandro Melo
d74b9604e3 Modified the new search for files of $readmem[hb] to be backward compatible 
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
 2020-01-31 22:10:51 -03:00
Rodrigo Alejandro Melo
7b3fe404ab $readmem[hb] file inclusion is now relative to the Verilog file 
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
 2020-01-31 18:20:22 -03:00
Claire Wolf
2ce7a0d369
Merge pull request #1667 from YosysHQ/clifford/verificnand 
Add Verific support for OPER_REDUCE_NAND
 2020-01-30 19:55:53 +01:00
Claire Wolf
60876ce183
Merge pull request #1503 from YosysHQ/eddie/verific_help 
`verific` pass to print help message when command syntax error
 2020-01-30 18:05:16 +01:00
Claire Wolf
ffadaddab5
Merge pull request #1654 from YosysHQ/eddie/sby_fix69 
verific: unflatten struct ports
 2020-01-30 18:03:35 +01:00
Claire Wolf
23c44afaed Add Verific support for OPER_REDUCE_NAND 
Signed-off-by: Claire Wolf <clifford@clifford.at>
 2020-01-30 18:01:13 +01:00
Eddie Hung
6d27d43727 Add and use SigSpec::reverse() 2020-01-28 10:37:16 -08:00
Eddie Hung
ce6a690d27 xilinx/ice40/ecp5: undo permuting LUT masks in lut_map 
Now done in read_aiger
 2020-01-27 13:30:27 -08:00
Eddie Hung
f443695a38 Merge remote-tracking branch 'origin/master' into eddie/verific_help 2020-01-27 10:34:10 -08:00
Eddie Hung
d730bba6d2 verific: no help() when no YOSYS_ENABLE_VERIFIC 2020-01-27 10:32:18 -08:00
Eddie Hung
7b445121cc verific: also unflatten for 'hierarchy' flow as per @cliffordwolf 2020-01-27 10:15:22 -08:00
Eddie Hung
c7fbe13db5 read_aiger: set abc9_box_seq attr 2020-01-24 13:11:43 -08:00
Eddie Hung
cccc0ae112 verific: unflatten struct ports 2020-01-24 10:12:52 -08:00
Eddie Hung
73526a6f10 read_aiger: also parse abc9_mergeability 2020-01-22 14:21:25 -08:00
Eddie Hung
cd093c00f8 read_aiger: discard LUT inputs with nodeID == 0; not < 2 2020-01-21 11:56:30 -08:00
Eddie Hung
7f728bc116 read_aiger: ignore constant inputs on LUTs 2020-01-21 11:16:50 -08:00
David Shah
22c967e35e ast: Add support for $sformatf system function 
Signed-off-by: David Shah <dave@ds0.me>
 2020-01-19 21:20:17 +00:00
Eddie Hung
03ce2c72bb Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor 2020-01-15 16:42:16 -08:00
Eddie Hung
05c8858a90 read_aiger: $lut prefix in front 2020-01-15 14:31:32 -08:00
Eddie Hung
53a99ade9c Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor 2020-01-14 11:46:56 -08:00
Eddie Hung
f63f76c372 read_aiger: also rename "$0" 2020-01-14 09:01:53 -08:00
Eddie Hung
2c65e1abac abc9: break SCC by setting (* keep *) on output wires 2020-01-13 21:45:27 -08:00
Eddie Hung
ee95fa959a read_aiger: uniquify wires with $aiger<autoidx> prefix 2020-01-13 21:28:27 -08:00
Eddie Hung
766e16b525 read_aiger: make $and/$not/$lut the prefix not suffix 2020-01-13 17:34:37 -08:00
Eddie Hung
d979648b7a read_aiger: more accurate debug message 2020-01-09 10:02:19 -08:00
Eddie Hung
943ea4bf9e read_aiger: do not double-count outputs for flops 2020-01-09 08:55:36 -08:00
Eddie Hung
2ca8c10e7a Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor 2020-01-07 15:43:22 -08:00
Eddie Hung
2ac36031d4 read_aiger: consistency between ascii and binary; also name latches 2020-01-07 13:30:31 -08:00
Eddie Hung
8f5388ea5b read_aiger fixes 2020-01-07 11:59:57 -08:00
Eddie Hung
b94cf0c126 read_aiger: connect identical signals together 2020-01-07 11:43:28 -08:00
Eddie Hung
baba33fbd3 read_aiger: cope with latches and POs with same name 2020-01-07 11:22:48 -08:00
Eddie Hung
738af17a26 read_aiger: default -clk_name to be empty 2020-01-07 11:21:45 -08:00
Eddie Hung
61a2a60595 read_aiger: do not process box connections, work standalone 2020-01-07 09:48:11 -08:00
Eddie Hung
b57f692a9e read_aiger: consistency between ascii and binary 2020-01-07 09:32:34 -08:00
Eddie Hung
83616e7866 read_aiger: add -xaiger option 2020-01-06 12:43:29 -08:00