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sv: Add lexing and parsing of .* (wildcard port conns)

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Signed-off-by: David Shah <dave@ds0.me>
This commit is contained in:
David Shah 2019-11-22 08:24:01 +00:00
parent 9f5613100b
commit 50f86c11b2
2 changed files with 6 additions and 1 deletions
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2
frontends/verilog/verilog_lexer.l
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@ -431,6 +431,8 @@ import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ {
"+:" { return TOK_POS_INDEXED; }
"-:" { return TOK_NEG_INDEXED; }
".*" { return TOK_AUTOCONNECT_ALL; }
[-+]?[=*]> {
if (!specify_mode) REJECT;
frontend_verilog_yylval.string = new std::string(yytext);

5
frontends/verilog/verilog_parser.y
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@ -138,7 +138,7 @@ struct specify_rise_fall {
%token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END
%token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM
%token TOK_PACKAGE TOK_ENDPACKAGE TOK_PACKAGESEP
%token TOK_INTERFACE TOK_ENDINTERFACE TOK_MODPORT TOK_VAR
%token TOK_INTERFACE TOK_ENDINTERFACE TOK_MODPORT TOK_VAR TOK_AUTOCONNECT_ALL
%token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_WAND TOK_WOR TOK_REG TOK_LOGIC
%token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_ALWAYS TOK_INITIAL
%token TOK_ALWAYS_FF TOK_ALWAYS_COMB TOK_ALWAYS_LATCH
@ -1580,6 +1580,9 @@ cell_port:
node->children.back()->str = *$3;
delete $3;
free_attr($1);
} |
attr TOK_AUTOCONNECT_ALL {
astbuf2->attributes[ID(autoconnect)] = AstNode::mkconst_int(1, false);
};
always_comb_or_latch: