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4094 commits 95 branches 53 tags 45 MiB
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Author SHA1 Message Date
Clifford Wolf
142f4ca03a Add timing constraints to osu035 example 2017-10-10 13:32:04 +02:00
Clifford Wolf
bc80426d45 Remove some dead code 2017-10-10 12:00:48 +02:00
Clifford Wolf
caa78388cd Allow $past, $stable, $rose, $fell in $global_clock blocks 2017-10-10 11:59:32 +02:00
Clifford Wolf
adf1754729 Add $shiftx support to verilog front-end 2017-10-07 13:40:54 +02:00
Clifford Wolf
2b04e8caa6 Update ABC to hg rev 0fc1803a77c0 2017-10-06 10:07:33 +02:00
Larry Doolittle
50bcd9a728 Clean whitespace and permissions in techlibs/intel 2017-10-05 16:23:49 +02:00
Clifford Wolf
fc3378916d Improve handling of Verific errors 2017-10-05 14:38:32 +02:00
Clifford Wolf
ee56a887b6 Improve Verific error handling, check VHDL static asserts 2017-10-04 18:56:28 +02:00
Clifford Wolf
3f22f48eeb Add blackbox command 2017-10-04 18:30:42 +02:00
Clifford Wolf
b92ff2706e Fix nasty bug in Verific bindings 2017-10-04 17:23:42 +02:00
Clifford Wolf
a381188b92 Merge branch 'pr_ast_const_funcs' of https://github.com/udif/yosys 2017-10-03 18:23:45 +02:00
Clifford Wolf
983479f395 Merge branch 'fix_shift_reduce_conflict' of https://github.com/udif/yosys 2017-10-03 18:20:08 +02:00
Clifford Wolf
b4fd7ecd83 Merge branch 'dh73-master' 2017-10-03 17:33:43 +02:00
Clifford Wolf
65f91e5120 Rename "write_verilog -nobasenradix" to "write_verilog -decimal" 2017-10-03 17:31:21 +02:00
dh73
4718e65763 Tested and working altsyncarm without init files 2017-10-01 19:59:45 -05:00
dh73
e480847753 Fixed wrong declaration in Verilog backend 2017-10-01 11:11:32 -05:00
dh73
cbaba62401 Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now 2017-10-01 11:04:17 -05:00
Udi Finkelstein
eb40278a16 Turned a few member functions into const, esp. dumpAst(), dumpVlog(). 2017-09-30 07:37:38 +03:00
Udi Finkelstein
72a08eca3d Resolved classical Bison IF/THEN/ELSE shift/reduce conflict using the textbook solution 
(Oreilly 'Flex & Bison' page 189)
 2017-09-30 06:39:07 +03:00
Clifford Wolf
c5b204d8d2 Add first draft of eASIC back-end 2017-09-29 17:53:43 +02:00
Clifford Wolf
e64b9d5a4d Fix synth_ice40 doc regarding -top default 2017-09-29 17:52:57 +02:00
Clifford Wolf
dbfd8460a9 Allow $size and $bits in verilog mode, actually check test case 2017-09-29 11:56:43 +02:00
Clifford Wolf
637a02eb5c Merge pull request #425 from udif/udif_dollar_bits 
Add $bits() and $size()
 2017-09-29 11:39:36 +02:00
Clifford Wolf
29f8acf095 Merge pull request #421 from stephengroat/osx-travis 
Add osx tests using brew bundle
 2017-09-28 14:45:47 +02:00
Stephen
57b3c34e69 delete bad backslash 2017-09-27 16:52:20 -07:00
Stephen
1ba06cefcc forgot to install bundles 2017-09-27 16:51:50 -07:00
Stephen Groat
de0797f073 Add osx tests using brew bundle 2017-09-27 16:49:03 -07:00
Clifford Wolf
30396270a2 Increase maximum LUT size in blifparse to 12 bits 2017-09-27 15:27:42 +02:00
Udi Finkelstein
e951ac0dfb $size() now works correctly for all cases! 
It seems the issues was that AST_MULTIRANGE is converted into a multirange_dimensions[] array on the AST_MEMORY node directly.
 2017-09-26 20:34:24 +03:00
Udi Finkelstein
6ddc6a7af4 $size() seems to work now with or without the optional parameter. 
Multidimensional arrays still don't work. I suspect the problem is that the array is flattened into a 1D array before $size() is evaluated.
 2017-09-26 19:18:25 +03:00
Clifford Wolf
91d9c50bb3 Parse reals as string in JSON front-end 2017-09-26 14:37:03 +02:00
Clifford Wolf
660473a485 Merge branch 'vlogpp-inc-fixes' 2017-09-26 14:02:57 +02:00
Clifford Wolf
2c04d883b1 Minor coding style fix 2017-09-26 13:50:14 +02:00
Clifford Wolf
cb1d439d10 Merge branch 'master' of https://github.com/combinatorylogic/yosys into combinatorylogic-master 2017-09-26 13:48:13 +02:00
Udi Finkelstein
7e391ba904 enable $bits() and $size() functions only when the SystemVerilog flag is enabled for read_verilog 2017-09-26 09:19:56 +03:00
Udi Finkelstein
2dea42e903 Added $bits() for memories as well. 2017-09-26 09:11:25 +03:00
Udi Finkelstein
17f8b41605 $size() now works with memories as well! 2017-09-26 08:36:45 +03:00
Udi Finkelstein
64eb8f29ad Add $size() function. At the moment it works only on expressions, not on memories. 2017-09-26 06:25:42 +03:00
Clifford Wolf
2cc09161ff Fix ignoring of simulation timings so that invalid module parameters cause syntax errors 2017-09-26 01:52:59 +02:00
combinatorylogic
64ca0be971 Adding support for string macros and macros with arguments after include 2017-09-21 18:25:02 +01:00
Clifford Wolf
143c0abd33 Merge pull request #413 from azonenberg/extract-reduce-tweaks 
Added support for off-chain loads in extract_reduce
 2017-09-16 11:31:37 +02:00
Andrew Zonenberg
2b65b65d70 Added missing "break" 2017-09-15 17:54:52 -07:00
Andrew Zonenberg
7b3966714c Implemented off-chain support for extract_reduce 2017-09-15 13:59:18 -07:00
Andrew Zonenberg
3404934c9c extract_reduce now only removes the head of the chain, relying on "clean" to delete upstream cells. Added "-allow-off-chain" flag, but it's currently ignored. 2017-09-15 13:59:05 -07:00
Clifford Wolf
5c4ea1366f Merge branch 'master' of github.com:cliffordwolf/yosys 2017-09-15 21:28:16 +02:00
Clifford Wolf
76c11d7454 Update ABC to hg rev cd6984ee82d4 2017-09-15 21:25:59 +02:00
Clifford Wolf
ce78717e36 Merge pull request #412 from azonenberg/reduce-fixes 
extract_reduce: Fix segfault on "undriven" inputs
 2017-09-14 22:36:25 +02:00
Robert Ou
ab1bf8d661 extract_reduce: Fix segfault on "undriven" inputs 
This is easily triggered when un-techmapping if the technology-specific
cell library isn't loaded. Outputs of technology-specific cells will be
seen as inputs, and nets using those outputs will be seen as undriven.
Just ignore these cells because they can't be part of a reduce chain
anyways.
 2017-09-14 12:54:44 -07:00
Clifford Wolf
498526cc0b Merge pull request #411 from azonenberg/counter-extraction-fixes 
Various improvements and bug fixes to extract_counter
 2017-09-14 21:44:26 +02:00
Clifford Wolf
b0b2f3fe29 Merge pull request #410 from azonenberg/opt_demorgan 
Added "opt_demorgan" pass (fixes #408)
 2017-09-14 21:42:34 +02:00