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Merge branch 'master' of github.com:cliffordwolf/yosys

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This commit is contained in:
Clifford Wolf 2017-09-15 21:28:16 +02:00
parent 76c11d7454 ce78717e36
commit 5c4ea1366f
1 changed files with 2 additions and 2 deletions
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4
passes/techmap/extract_reduce.cc
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@ -160,7 +160,7 @@ struct ExtractReducePass : public Pass
if (sig_to_sink[a[0]].size() + port_sigs.count(a[0]) == 1)
{
Cell* cell_a = sig_to_driver[a[0]];
if (((cell_a->type == "$_AND_" && gt == GateType::And) ||
if (cell_a && ((cell_a->type == "$_AND_" && gt == GateType::And) ||
(cell_a->type == "$_OR_" && gt == GateType::Or) ||
(cell_a->type == "$_XOR_" && gt == GateType::Xor)))
{
@ -177,7 +177,7 @@ struct ExtractReducePass : public Pass
if (sig_to_sink[b[0]].size() + port_sigs.count(b[0]) == 1)
{
Cell* cell_b = sig_to_driver[b[0]];
if (((cell_b->type == "$_AND_" && gt == GateType::And) ||
if (cell_b && ((cell_b->type == "$_AND_" && gt == GateType::And) ||
(cell_b->type == "$_OR_" && gt == GateType::Or) ||
(cell_b->type == "$_XOR_" && gt == GateType::Xor)))
{