Jannis Harder
2a68eee5f1
xprop: Test fixes and abort on test failure
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Use `$finish(0)` to silently exit even when using recent iverlog
versions. Run `write_verilog -noexpr` before `write_verilog` as the
latter can modify the design.
This also enables checking the tests results, as xprop should be in a
state where the existing tests pass.
2023-02-13 14:05:16 +01:00
Jannis Harder
9f20beb7df
xprop: Smaller subset of tests to run by default
2023-02-13 14:02:02 +01:00
Jannis Harder
160eeab2bb
verilog_backend: Do not run bwmuxmap even if in expr mode
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While bwmuxmap generates equivalent logic, it doesn't propagate x bits
in the same way, which can be relevant when writing verilog.
2023-02-13 14:00:38 +01:00
Jannis Harder
1698202ccc
sim: For yw cosim, drive parent module's signals for input ports
2023-02-13 12:26:06 +01:00
github-actions[bot]
4c334b905f
Bump version
2023-02-13 00:17:46 +00:00
Dag Lem
615adc4253
Resolve package types in interfaces ( #3658 )
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* Resolve package types in interfaces
* Added test for resolving of package types in interfaces
2023-02-12 18:25:39 -05:00
Zachary Snow
26a6c60478
Add test for typenames using constants shadowed later on
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This possible edge case came up while reviewing #3555 . It is currently
handled correctly, but there is no clear test coverage.
2023-02-12 17:03:37 -05:00
github-actions[bot]
5ea2c290a5
Bump version
2023-02-11 00:14:42 +00:00
Jannis Harder
6d021f04d4
tests: Fix path of yosys invocation in xprop tests
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For now xprop test failures are still expected and ignored, but without
this change, they did not even run unless the yosys build was in path.
2023-02-10 19:17:16 +01:00
Jannis Harder
f3c4e93d24
Merge pull request #3667 from jix/xprop-test-make-fix
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tests: in xprop tests, use MAKE variable if set
2023-02-10 16:06:16 +01:00
Jannis Harder
d31d5da69f
tests: in xprop tests, use MAKE variable if set
2023-02-10 15:01:04 +01:00
github-actions[bot]
b1a011138c
Bump version
2023-02-09 01:17:36 +00:00
Miodrag Milanovic
a7099b0a72
Next dev cycle
2023-02-08 12:34:19 +01:00
Miodrag Milanovic
7e588664e7
Release version 0.26
2023-02-08 12:32:43 +01:00
Jannis Harder
ddb2bd85c8
Merge pull request #3662 from YosysHQ/micko/wide_case_select_box
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Add Verific import support for OPER_WIDE_CASE_SELECT_BOX
2023-02-08 12:22:30 +01:00
Miodrag Milanovic
5f33c0e0b2
Updated changelog
2023-02-08 10:11:47 +01:00
Miodrag Milanovic
109b88c379
For case select values use Sa instead of Sx and Sz
2023-02-08 09:22:48 +01:00
uis
ea6f562d49
gowin: Add new types of oscillator
2023-02-06 21:34:32 +00:00
N. Engelhardt
417fadbefd
Merge pull request #3625 from povik/show_cleanup
2023-02-06 16:11:26 +01:00
Miodrag Milanovic
e7e37df91b
Add verific import support for OPER_WIDE_CASE_SELECT_BOX
2023-02-06 09:28:23 +01:00
Dag Lem
777c589e85
Handle range offsets in packed arrays within packed structs
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This brings the metadata for packed arrays in packed structs
in line with the metadata for unpacked arrays, and correctly
handles the case when both lsb and msb in an address range are
non-zero.
2023-02-05 17:09:51 +01:00
github-actions[bot]
45edc8eb98
Bump version
2023-02-05 00:18:39 +00:00
Catherine
5fa96ccdee
Merge pull request #3659 from whitequark/update-abc
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Bump ABCREV to fix WASM build
2023-02-04 04:09:55 +00:00
Catherine
3af3cc15b5
Bump ABCREV to fix WASM build.
2023-02-04 03:35:53 +00:00
github-actions[bot]
54bf15a5b8
Bump version
2023-02-04 00:16:33 +00:00
Aki Van Ness
a90f940615
backends/firrtl: Ensure modInstance is valid
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This should fix #3648 where when calling `emit_elaborated_extmodules` it
checks to see if a module is a black-box, however there was no
validation that the cell type was actually known, and it just always
assumed that we would get a valid instance, causing a segfault.
2023-02-03 08:27:52 -05:00
github-actions[bot]
221036c5b6
Bump version
2023-02-02 00:17:21 +00:00
Jannis Harder
0f2cb80a26
Merge pull request #3655 from jix/smt2_fix_b_op_width
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smt2: Fix operation width computation for boolean producing cells
2023-02-01 18:06:59 +01:00
Jannis Harder
5e82638408
smt2: Fix operation width computation for boolean producing cells
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The output width for the boolean value should not influence the
operation width. The previous incorrect width extension would still
produce correct results, but could produce invalid smt2 output for
reduction operators when the output width was larger than the width of
the vector to which the reduction was applied.
This fixes #3654
2023-02-01 12:34:35 +01:00
github-actions[bot]
f7c1e4aadf
Bump version
2023-01-31 00:17:36 +00:00
Jannis Harder
c235802f4a
Merge pull request #3650 from jix/rtlil_roundtrip_z_bits
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backends/rtlil: Do not shorten a value with z bits to 'x
2023-01-30 16:14:24 +01:00
N. Engelhardt
419f91a2b9
add option to fsm_detect to ignore self-resetting
2023-01-30 16:12:53 +01:00
N. Engelhardt
ecfa7e9fbc
add pmux option to bmuxmap for better fsm detection with verific frontend
2023-01-30 16:12:53 +01:00
martell
dbc8b77222
gowin: Add support for emulated differential output
2023-01-29 20:48:43 -08:00
github-actions[bot]
d11cb6901f
Bump version
2023-01-30 00:14:47 +00:00
Dag Lem
26db5a11d3
Resolve struct member package types
2023-01-29 13:51:44 -05:00
Dag Lem
db13c6df2b
Handle struct members of union type ( #3641 )
2023-01-29 13:45:45 -05:00
Jannis Harder
b08a880704
backends/rtlil: Do not shorten a value with z bits to 'x
2023-01-29 14:02:25 +01:00
Lofty
822c7b0341
muxcover: do not add decode muxes with x inputs
2023-01-26 05:19:45 +00:00
github-actions[bot]
541fdffff2
Bump version
2023-01-26 00:16:37 +00:00
Miodrag Milanović
b9155a574e
Merge pull request #3647 from jix/formalff-hierarchy-fix
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formalff: Fix crash with _NOT_ gates in -hierarchy mode
2023-01-25 13:37:44 +01:00
Jannis Harder
afac3f2c76
formalff: Fix crash with _NOT_ gates in -hierarchy mode
2023-01-25 12:55:29 +01:00
github-actions[bot]
755b753e1a
Bump version
2023-01-24 00:16:28 +00:00
Miodrag Milanović
8180cc4325
Merge pull request #3624 from jix/sim_yw
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Changes to support SBY trace generation with the sim command
2023-01-23 16:55:17 +01:00
Miodrag Milanović
245884a101
Merge pull request #3629 from YosysHQ/micko/clang_fixes
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Fixes for some of clang scan-build detected issues
2023-01-23 16:24:22 +01:00
Miodrag Milanović
9bc9121b9e
Merge pull request #3636 from YosysHQ/log_plugin
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Call yosys_shutdown to properly cleanup plugins and tcl when expecting error
2023-01-23 16:24:03 +01:00
gatecat
bfacaddca8
show: Remove left-in debug log_warning
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Signed-off-by: gatecat <gatecat@ds0.me>
2023-01-23 13:54:07 +01:00
Miodrag Milanovic
200ffdccc5
Call yosys_shutdown to properly cleanup plugins and tcl when expecting error
2023-01-20 16:09:42 +01:00
Miodrag Milanović
611f71c670
Merge pull request #3630 from yrabbit/gw1n4c-pll
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gowin: add a new type of PLL - PLLVR
2023-01-18 08:30:29 +01:00
github-actions[bot]
29e7756b0c
Bump version
2023-01-18 00:17:17 +00:00
