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Code Activity
2304 commits 102 branches 53 tags 48 MiB
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Author SHA1 Message Date
Clifford Wolf
caa274ada6 Added design->rename(module, new_name) 2015-06-30 01:37:59 +02:00
Clifford Wolf
df0163cd2b iCE40: set min bram efficiency to 2% 2015-06-20 09:31:19 +02:00
Clifford Wolf
94fbaff58f Using static mem size of 128 MB in emcc build 2015-06-20 08:58:02 +02:00
Clifford Wolf
3123c45415 Added init support to SMV back-end 2015-06-19 16:43:02 +02:00
Clifford Wolf
6c6bf4999e Progress in SMV back-end 2015-06-19 16:26:53 +02:00
Clifford Wolf
8c79765de5 Progress in SMV back-end 2015-06-19 14:08:46 +02:00
Clifford Wolf
8a86162ae9 Progress in SMV back-end 2015-06-18 16:29:11 +02:00
Clifford Wolf
8e84418225 Progress in SMV back-end 2015-06-17 09:56:42 +02:00
Clifford Wolf
99100f367d Added "rename -top new_name" 2015-06-17 09:38:56 +02:00
Clifford Wolf
9f7a5b4ef9 Progress in SMV back-end 2015-06-17 07:24:27 +02:00
Clifford Wolf
b8c5e27006 Progress in SMV back-end 2015-06-16 19:05:26 +02:00
Clifford Wolf
ed128b82d7 Added "synth -nordff -noalumacc" 2015-06-15 17:07:40 +02:00
Clifford Wolf
52315039c5 Progress in SMV back-end 2015-06-15 17:01:01 +02:00
Clifford Wolf
0f01ef61ef Progress in SMV back-end 2015-06-15 13:24:17 +02:00
Clifford Wolf
ea23bb8aa4 Added "write_smv" skeleton 2015-06-15 00:46:27 +02:00
Clifford Wolf
93685a77c6 Removed debug code from write_smt2 2015-06-14 16:22:06 +02:00
Clifford Wolf
66910e15b2 Modernized memory_dff (and fixed a bug) 2015-06-14 16:15:51 +02:00
Clifford Wolf
f6eca509bb Added "memory -nordff" 2015-06-14 15:47:11 +02:00
Clifford Wolf
255dcb27a0 Added write_smt2 -mem 2015-06-14 15:46:47 +02:00
Clifford Wolf
285f140f60 Makefile fix for YosysJS build 2015-06-11 15:48:40 +02:00
Clifford Wolf
4c733301e6 Fixed cstr_buf for std::string with small string optimization 2015-06-11 13:39:49 +02:00
Clifford Wolf
3a6abc9bf6 Improvements in cellaigs.cc and "json -aig" 2015-06-11 10:48:16 +02:00
Clifford Wolf
1ae360cf72 AigMaker refactoring 2015-06-10 23:00:12 +02:00
Clifford Wolf
e534881794 Added "json -aig" 2015-06-10 08:13:56 +02:00
Clifford Wolf
56d4822719 Renamed "aig" to "aigmap" 2015-06-10 07:24:26 +02:00
Clifford Wolf
85287295b2 Fixed cellaigs port extending 2015-06-10 07:16:30 +02:00
Clifford Wolf
66f9ee412a Added "aig" pass 2015-06-09 22:33:26 +02:00
Clifford Wolf
9500b564ac synth_ice40 now flattens by default 2015-06-09 20:28:17 +02:00
Clifford Wolf
e49e2662aa Added cellaigs API 2015-06-09 09:54:22 +02:00
Clifford Wolf
b57cb4a7fe Merge clock inverters in memory_dff 2015-06-09 07:25:12 +02:00
Clifford Wolf
c88be7bae5 Merge branch 'verilog-backend-memV2' of github.com:wluker/yosys 2015-06-09 06:42:07 +02:00
luke whittlesey
2f90499e3d $mem cell in verilog backend : grouped writes by clock 2015-06-08 17:35:40 -04:00
Clifford Wolf
de4f4dad3c Fixed "avail_parameters" handling in module clone/copy 2015-06-08 14:49:34 +02:00
Clifford Wolf
98650a0609 Added log_dump() support for IdStrings 2015-06-08 14:49:02 +02:00
Clifford Wolf
13983e8318 Fixed handling of parameters with reversed range 2015-06-08 14:03:06 +02:00
luke whittlesey
a8fe040906 Bug fix in $mem verilog backend + changed tests/bram flow of make test. 2015-06-04 16:12:40 -04:00
Clifford Wolf
08f9b38a9c Added opt_share -share_all 2015-05-31 14:24:34 +02:00
Clifford Wolf
09ef279b60 Added iCE40 PLL cells 2015-05-31 13:10:43 +02:00
Clifford Wolf
522705cc28 Added liberty dont_use support to dfflibmap 2015-05-31 07:51:12 +02:00
Clifford Wolf
99b8746d27 Fixed signedness of genvar expressions 2015-05-29 20:08:00 +02:00
Clifford Wolf
c329233f0d Added output args to synth_ice40 2015-05-26 17:08:53 +02:00
Clifford Wolf
08a4af3cde Improvements in BLIF front-end 2015-05-24 08:03:21 +02:00
Clifford Wolf
313f570fcc improved ice40 SB_IO sim model 2015-05-23 10:17:03 +02:00
Clifford Wolf
9f772eb970 Improved "flatten" handlings of inout ports 2015-05-23 10:14:53 +02:00
Clifford Wolf
4b6221478e Added simple $dlatch support to opt_rmdff 2015-05-23 09:45:48 +02:00
Clifford Wolf
264eb8eb6e Added ice40 SB_IO sim model 2015-05-23 09:30:24 +02:00
Clifford Wolf
98bceed0da Merge branch 'master' of github.com:cliffordwolf/yosys 2015-05-22 08:23:03 +02:00
Clifford Wolf
e122c2644e preserve used $-wires with init attribute in opt_clean 2015-05-22 08:20:29 +02:00
Clifford Wolf
4744bb95fb Some fixes for $mem in verilog back-end 2015-05-20 13:55:50 +02:00
Clifford Wolf
6061b7bd58 bugfix in blif front-end 2015-05-18 11:15:49 +02:00