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5219 commits 122 branches 59 tags 72 MiB
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Author SHA1 Message Date
Clifford Wolf
c9949dba99
Merge pull request #1117 from bwidawsk/more-home 
Add a few more filename rewrites
 2019-06-21 10:13:51 +02:00
Clifford Wolf
78e7a6f6f2
Merge pull request #1119 from YosysHQ/eddie/fix1118 
Make genvar a signed type
 2019-06-21 10:13:13 +02:00
Clifford Wolf
86a753cc18
Merge pull request #1116 from YosysHQ/eddie/fix1115 
Sign extend unsized 'bx and 'bz values
 2019-06-21 10:12:32 +02:00
Eddie Hung
c4ea6fff65 Fix gcc invalidation behaviour for write_aiger 2019-06-20 21:56:47 -07:00
Eddie Hung
c20adc5263 Add test 2019-06-20 16:07:22 -07:00
Eddie Hung
c27ab609fa Make genvar a signed type 2019-06-20 16:04:12 -07:00
Eddie Hung
3b8f3a93ad Add CHANGELOG entry 2019-06-20 12:45:40 -07:00
Eddie Hung
d0bbf9e4d4 Extend sign extension tests 2019-06-20 12:43:59 -07:00
Eddie Hung
20119ee50e Maintain "is_unsized" state of constants 2019-06-20 12:43:39 -07:00
Eddie Hung
e33cbb0dde Revert "Fix sign extension when sign is 1'bx" 
This reverts commit 0221f3e1c5.
 2019-06-20 12:40:05 -07:00
Ben Widawsky
8767ec3fbd Add a few more filename rewrites 
This now allows a full pipeline to work, something such as:
yosys -p "synth_ecp5 -json ~/work/fpga/prjtrellis/examples/ecp5_evn/blinky.v"

Otherwise, you will get something along the lines of:
ERROR: Can't open output file `~/work/fpga/prjtrellis/examples/ecp5_evn/blinky.v' for writing: No such file or directory

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
 2019-06-20 10:27:59 -07:00
Eddie Hung
b77322034c Remove leftover comment 2019-06-20 10:15:04 -07:00
Eddie Hung
b98276fa61 Add test 2019-06-20 10:13:52 -07:00
Eddie Hung
0221f3e1c5 Fix sign extension when sign is 1'bx 2019-06-20 10:13:52 -07:00
Clifford Wolf
477e566e8d Fix typo, fixes #1095 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-20 15:34:52 +02:00
Clifford Wolf
06eb87bcb7 Improve shregmap help message, fixes #1113 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-20 15:23:55 +02:00
Clifford Wolf
a8c85d1b4b Update some .gitignore files 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-20 14:27:57 +02:00
Clifford Wolf
11ec7b2aec Fix typo 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-20 12:23:07 +02:00
Clifford Wolf
7f1461d64b Merge branch 'towoe-unpacked_arrays' 2019-06-20 12:06:58 +02:00
Clifford Wolf
6a6dd5e057 Add proper test for SV-style arrays 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-20 12:06:07 +02:00
Clifford Wolf
2428fb7dc2 Merge branch 'unpacked_arrays' of https://github.com/towoe/yosys-sv into towoe-unpacked_arrays 2019-06-20 12:03:00 +02:00
Eddie Hung
3b1e5264d8
Merge pull request #1111 from acw1251/help_summary_fixes 
Fixed the help summary line for a few commands
 2019-06-19 15:30:50 -07:00
acw1251
ce29ede801 Fixed small typo in ice40_unlut help summary 2019-06-19 16:39:46 -04:00
acw1251
0d888ee7ed Fixed the help summary line for a few commands 2019-06-19 15:27:04 -04:00
Eddie Hung
96ade54993 Fix bug in #1078, add entry to CHANGELOG 2019-06-19 09:51:11 -07:00
Clifford Wolf
8395f837c3
Merge pull request #1109 from YosysHQ/clifford/fix1106 
Add "read_verilog -pwires" feature
 2019-06-19 17:25:39 +02:00
Clifford Wolf
ec4565009a Add "read_verilog -pwires" feature, closes #1106 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-19 14:38:50 +02:00
Clifford Wolf
5a1f1caa44
Merge pull request #1105 from YosysHQ/clifford/fixlogicinit 
Improve handling of initial/default values
 2019-06-19 13:53:07 +02:00
Tobias Wölfel
8b8af10f5e Unpacked array declaration using size 
Allows fixed-sized array dimension specified by a single number.

This commit is based on the work from PeterCrozier
https://github.com/YosysHQ/yosys/pull/560.
But is split out of the original work.
 2019-06-19 12:47:48 +02:00
Clifford Wolf
c330379870 Make tests/aiger less chatty 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-19 12:20:35 +02:00
Clifford Wolf
fa5fc3f6af Add defvalue test, minor autotest fixes for .sv files 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-19 12:12:08 +02:00
Clifford Wolf
3da5288ce0 Use input default values in hierarchy pass 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-19 11:49:20 +02:00
Clifford Wolf
8d0cd529c9 Add defaultvalue attribute 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-19 11:37:11 +02:00
Clifford Wolf
6d64e242ba Fix handling of "logic" variables with initial value 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-19 11:25:11 +02:00
Clifford Wolf
b3441935b1
Merge pull request #1100 from bwidawsk/home 
Support ~ in filename parsing
 2019-06-19 10:52:59 +02:00
Clifford Wolf
eb3b9fb24a
Merge pull request #1104 from whitequark/case-semantics 
Clarify switch/case semantics in RTLIL
 2019-06-19 10:50:32 +02:00
whitequark
addf01d45d Explain exact semantics of switch and case rules in the manual. 2019-06-19 05:22:40 +00:00
whitequark
df6576edc8 In RTLIL::Module::check(), check process invariants. 2019-06-19 05:22:13 +00:00
Ben Widawsky
4a18e19fb8 Support filename rewrite in backends 
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
 2019-06-18 14:39:52 -07:00
Ben Widawsky
468c41d997 Support ~ for home directory 
This is tested on Linux only

v2:
Wrap functioanlity in ifndef _WIN32 (eddiehung)
Find '~/' instead of '~' (cliffordwolf)

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
 2019-06-18 14:38:40 -07:00
Clifford Wolf
64947453e2
Merge pull request #1086 from udif/pr_elab_sys_tasks2 
Fixed broken $error()/$info/$warning() on non-generate blocks (within always/initial blocks)
 2019-06-18 16:52:08 +02:00
Clifford Wolf
c23bbc4291 Add timescale and generated-by header to yosys-smtbmc MkVcd 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-16 23:12:03 +02:00
Serge Bazanski
d4f77d408c
Merge pull request #829 from abdelrahmanhosny/master 
Dockerfile for Yosys
 2019-06-13 12:14:37 +02:00
Udi Finkelstein
4b56f6646d Fixed brojen $error()/$info/$warning() on non-generate blocks 
(within always/initial blocks)
 2019-06-11 02:52:06 +03:00
Eddie Hung
a91ea6612a Add some more comments 2019-06-10 10:27:55 -07:00
David Shah
498c21e735
Merge pull request #1082 from corecode/u4k 
ice40/cells_sim.v: Add support for RGB_DRV/LED_DRV_CUR for u4k
 2019-06-10 15:12:23 +01:00
Simon Schubert
abf90b0403 ice40/cells_sim.v: Add support for RGB_DRV/LED_DRV_CUR for u4k 2019-06-10 11:49:08 +02:00
Clifford Wolf
5a5cbf6458
Merge pull request #1078 from YosysHQ/eddie/muxcover_costs 
Allow muxcover costs to be changed
 2019-06-08 11:31:19 +02:00
Eddie Hung
2b350401c4 Fix spacing from spaces to tabs 2019-06-07 15:44:57 -07:00
Clifford Wolf
7395a80690
Merge pull request #1079 from YosysHQ/eddie/fix_read_aiger 
Fix read_aiger to really get tested, and fix some uncovered read_aiger issues
 2019-06-07 23:13:34 +02:00