Eddie Hung
1ec5f18346
Cope with inout ports
2019-04-17 14:43:45 -07:00
Eddie Hung
2b860809e9
Stop topological sort at abc_flop_q
2019-04-17 12:28:19 -07:00
Eddie Hung
d59185f1d6
Remove init* from xaiger, also topo-sort cells for box flow
2019-04-17 11:08:42 -07:00
Eddie Hung
5c134980c4
Optimise
2019-04-16 21:05:44 -07:00
Eddie Hung
e7a8955818
CIs before PIs; also sort each cell's connections before iterating
2019-04-16 16:37:47 -07:00
Eddie Hung
55a3638c71
Port from xc7mux branch
2019-04-16 15:01:45 -07:00
Eddie Hung
fe0b421212
Output __const0__ and __const1__ CIs
2019-04-12 18:16:25 -07:00
Eddie Hung
686e772f0b
ci_bits and co_bits now a list, order is important for ABC
2019-04-12 16:17:48 -07:00
Eddie Hung
c748391730
WIP
2019-04-12 14:13:11 -07:00
Eddie Hung
2217d59e29
Add non-input bits driven by unrecognised cells as ci_bits
2019-04-10 18:06:33 -07:00
Eddie Hung
bca3cf6843
Merge branch 'master' into xaig
2019-04-08 16:31:59 -07:00
Jim Lawson
73b87e7807
Refine memory support to deal with general Verilog memory definitions.
2019-04-01 15:02:12 -07:00
Clifford Wolf
1eff8be8f0
Add support for memory initialization to write_btor
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-23 14:40:01 +01:00
Clifford Wolf
e78f5a3055
Fix BTOR output tags syntax in writye_btor
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-23 14:39:42 +01:00
Clifford Wolf
bacca57537
Fix smtbmc.py handling of zero appended steps
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-14 22:04:42 +01:00
Clifford Wolf
04e920337b
Fix a syntax bug in ilang backend related to process case statements
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-14 17:50:20 +01:00
Clifford Wolf
53b28b3f01
Merge pull request #869 from cr1901/win-shell
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Install launcher executable when running yosys-smtbmc on Windows.
2019-03-14 16:43:23 +01:00
William D. Jones
ff15cf9b1f
Install launcher executable when running yosys-smtbmc on Windows.
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Signed-off-by: William D. Jones <thor0505@comcast.net>
2019-03-13 13:49:16 -04:00
Clifford Wolf
20c6a8c9b0
Improve determinism of IdString DB for similar scripts
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-11 20:12:28 +01:00
Clifford Wolf
94f995ee37
Fix signed $shift/$shiftx handling in write_smt2
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-09 13:19:41 -08:00
Clifford Wolf
5dfc7becca
Use SVA label in smt export if available
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-07 11:31:46 -08:00
Jim Lawson
d6c4dfb902
Ensure fid() calls make_id() for consistency; tests/simple/dff_init.v fails
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Mark dff_init.v as expected to fail since it uses "initial value".
2019-03-04 13:37:23 -08:00
Clifford Wolf
03237de686
Fix "write_edif -gndvccy"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-01 12:59:07 -08:00
Clifford Wolf
241901461a
Add "write_verilog -siminit"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-28 15:03:03 -08:00
Larry Doolittle
e2fc18f27b
Reduce amount of trailing whitespace in code base
2019-02-28 14:58:11 -08:00
Clifford Wolf
6d143c9a01
Merge pull request #827 from ucb-bar/firrtlfixes
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Fix FIRRTL to Verilog process instance subfield assignment.
2019-02-28 14:45:04 -08:00
Clifford Wolf
f570aa5e1d
Fix smt2 code generation for partially initialized memowy words, fixes #831
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-02-28 12:15:58 -08:00
Eddie Hung
8e883d92ed
write_xaiger to behave for undriven/unused inouts
2019-02-26 12:17:51 -08:00
Eddie Hung
c492a3a1c4
write_xaiger duplicate inout port into out port with $inout.out suffix
2019-02-25 18:39:36 -08:00
Jim Lawson
171c425cf9
Fix FIRRTL to Verilog process instance subfield assignment.
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Don't emit subfield assignments: bits(x, y, z) <= ... - but instead, add them to the reverse-wire-map where they'll be treated at the end of the module.
Enable tests which were disabled due to incorrect treatment of subfields.
Assume the `$firrtl2verilog` variable contains any additional switches to control verilog generation (i.e. `--no-dedup -X mverilog`)
2019-02-25 16:18:13 -08:00
Eddie Hung
292f80d231
Cleanup abc9 code
2019-02-25 15:20:56 -08:00
Eddie Hung
5180338e80
write_xaiger to write __dummy_o__ for -symbols too
2019-02-21 17:03:18 -08:00
Eddie Hung
085ed9f487
Add attribution
2019-02-21 14:40:13 -08:00
Eddie Hung
2f96a0ed32
write_xaiger to use original bit for co, not sigmap()-ed bit
2019-02-21 11:15:25 -08:00
Eddie Hung
01f8d50ba2
Remove swap file
2019-02-20 16:17:01 -08:00
Eddie Hung
f89b112fbf
write_aiger: fix CI/CO and symbols
2019-02-20 15:35:32 -08:00
Eddie Hung
ef60ca1717
write_xaiger to not write latches, CO/PO fixes
2019-02-20 11:09:13 -08:00
Eddie Hung
f9af902532
Merge branch 'master' into xaig
2019-02-19 14:20:04 -08:00
Eddie Hung
11480b4fa3
Instead of INIT param on cells, use initial statement with hier ref as
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per @cliffordwolf
2019-02-17 12:18:12 -08:00
Eddie Hung
17cd5f759f
Merge https://github.com/YosysHQ/yosys into dff_init
2019-02-17 11:49:06 -08:00
Eddie Hung
30f1204721
Cleanup
2019-02-16 22:22:17 -08:00
Eddie Hung
76c35f80f4
Cleanup
2019-02-16 21:09:48 -08:00
Eddie Hung
6a57de9013
write_xaiger to support non-bit cell connections, and cope with COs for -O
2019-02-16 21:00:39 -08:00
Eddie Hung
b9a305b85d
write_aiger -O to write dummy output as __dummy_o__
2019-02-16 20:08:59 -08:00
Eddie Hung
0c409e6d8c
Tidy up write_xaiger
2019-02-16 08:48:33 -08:00
Eddie Hung
2c1655ae94
write_aiger() to perform CI/CO post-processing and fix symbols
2019-02-16 08:46:25 -08:00
Eddie Hung
486a270415
Fixes needed for DFF circuits
2019-02-15 15:22:18 -08:00
Jim Lawson
c245041bfe
Removed unused variables, functions.
2019-02-15 12:00:28 -08:00
Eddie Hung
3ac5b65197
write_xaiger to cope with unknown cells by transforming them to CI/CO
2019-02-15 11:51:21 -08:00
Jim Lawson
fc1c9aa11f
Update cells supported for verilog to FIRRTL conversion.
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Issue warning messages for missing parameterized modules and attempts to set initial values.
Replace simple "if (cell-type)" with "else if" chain.
Fix FIRRTL shift handling.
Add support for parameterized modules, $shift, $shiftx.
Handle default output file.
Deal with no top module.
Automatically run pmuxtree pass.
Allow EXTRA_FLAGS and SEED parameters to be set in the environment for tests/tools/autotest.mk.
Support FIRRTL regression testing in tests/tools/autotest.sh
Add xfirrtl files to test directories to exclude files from FIRRTL regression tests that are known to fail.
2019-02-15 11:14:17 -08:00
