102 commits

Author	SHA1	Message	Date
Eddie Hung	9b1078b9bd	Fix/workaround symptom unveiled by #1023	2019-05-21 18:50:02 -07:00
Eddie Hung	fb09c6219b	Merge remote-tracking branch 'origin/master' into xc7mux	2019-05-21 14:21:00 -07:00
Eddie Hung	c2e29ab809	Rename cells_map.v to prevent clash with ff_map.v	2019-05-03 14:40:32 -07:00
Eddie Hung	283e33ba5a	Trim off leading 1'bx in A	2019-05-02 16:02:37 -07:00
Eddie Hung	fc72f07efd	Add don't care optimisation	2019-05-02 15:01:37 -07:00
Eddie Hung	95867109ea	Revert to pre-muxcover approach	2019-05-02 11:25:10 -07:00
Eddie Hung	5cd19b52da	Merge remote-tracking branch 'origin/master' into xc7mux	2019-05-02 10:44:59 -07:00
Eddie Hung	af840bbc63	Move neg-pol to pos-pol mapping from ff_map to cells_map.v	2019-04-28 12:36:04 -07:00
Eddie Hung	4aca928033	Fix spacing	2019-04-26 19:46:34 -07:00
Eddie Hung	e31e21766d	Try a different approach with 'muxcover'	2019-04-26 16:09:54 -07:00
Eddie Hung	f14d7f0df6	Cleanup superseded	2019-04-25 19:43:41 -07:00
Eddie Hung	60026842b2	Tweak	2019-04-22 17:59:56 -07:00
Eddie Hung	26e461f47d	Fix for A_WIDTH == 2 but B_WIDTH==3	2019-04-22 17:58:28 -07:00
Eddie Hung	1fa2c36fbd	Trim A_WIDTH by Y_WIDTH-1	2019-04-22 17:14:11 -07:00
Eddie Hung	69863f7698	Add comment	2019-04-22 16:58:44 -07:00
Eddie Hung	61161faefc	Fix for mux_case_* mappings	2019-04-22 16:56:18 -07:00
Eddie Hung	ac1e13819e	Fix for non-pow2 width muxes	2019-04-22 14:26:13 -07:00
Eddie Hung	75b96b1aff	Add synth_xilinx -nomux option	2019-04-22 12:36:15 -07:00
Eddie Hung	4486a98fd5	Merge remote-tracking branch 'origin/xc7srl' into xc7mux	2019-04-22 11:45:49 -07:00
Eddie Hung	233edf00fe	Fix cells_map.v some more	2019-04-11 10:48:14 -07:00
Eddie Hung	8658b56a08	More fine tuning	2019-04-11 10:08:05 -07:00
Eddie Hung	0ec8564099	Fix cells_map.v	2019-04-11 10:04:58 -07:00
Eddie Hung	bca3779657	Fix typo	2019-04-11 09:25:19 -07:00
Eddie Hung	87b8d29a90	Juggle opt calls in synth_xilinx	2019-04-11 09:13:39 -07:00
Eddie Hung	cd7b2de27f	WIP for cells_map.v -- maybe working?	2019-04-10 18:05:09 -07:00
Eddie Hung	3d577586fd	Try splitting $shiftx with Y_WIDTH > 1 into Y_WIDTH = 1	2019-04-10 16:15:23 -07:00
Eddie Hung	3f5dab0d09	Fix for when B_SIGNED = 1	2019-04-10 14:51:10 -07:00
Eddie Hung	1ec949d5ed	Tidy up	2019-04-10 09:02:42 -07:00
Eddie Hung	e0b46eb4cb	WIP for $shiftx to wide mux	2019-04-10 08:49:55 -07:00
Eddie Hung	1d526b7f06	Call shregmap twice -- once for variable, another for fixed	2019-04-05 17:35:49 -07:00
Eddie Hung	544843da71	techmap inside map_cells stage	2019-04-05 12:55:52 -07:00
Eddie Hung	2fb02247a7	Use soft-logic, not LUT3 instantiation	2019-04-04 08:10:40 -07:00
Eddie Hung	77755b5a66	Cleanup comments	2019-04-04 07:41:40 -07:00
Eddie Hung	81c207fb9b	Fine tune cells_map.v	2019-03-20 10:55:14 -07:00
Eddie Hung	505e4c2d59	Revert $__SHREG_ to orig; use $__XILINX_SHREG for variable length	2019-03-19 21:58:05 -07:00
Eddie Hung	5445cd4d00	Add support for variable length Xilinx SRL > 128	2019-03-19 17:44:33 -07:00
Eddie Hung	9156e18f92	Fix spacing	2019-03-19 16:12:32 -07:00
Eddie Hung	f239cb821e	Fix INIT for variable length SRs that have been bumped up one	2019-03-19 14:54:43 -07:00
Eddie Hung	fadeadb8c8	Only accept <128 for variable length, only if $shiftx exclusive	2019-03-16 08:51:13 -07:00
Eddie Hung	29a8d4745e	Cleanup synth_xilinx	2019-03-15 23:01:40 -07:00
Eddie Hung	06f8f2654a	Working	2019-03-15 19:13:40 -07:00
Eddie Hung	e7ef7fa443	Reverse bits in INIT parameter for Xilinx, since MSB is shifted first	2019-03-14 09:38:42 -07:00
Eddie Hung	f1a8e8a480	Merge remote-tracking branch 'origin/master' into xc7srl	2019-03-14 08:59:19 -07:00
Eddie Hung	79b4a275ce	Fix cells_map for SRL	2019-03-14 08:09:48 -07:00
Eddie Hung	24f129ddfb	Refactor $__SHREG__ in cells_map.v	2019-03-13 16:17:54 -07:00
Keith Rothman	3090951d54	Changes required for VPR place and route synth_xilinx. ... Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>	2019-03-01 12:02:27 -08:00
Eddie Hung	8aab7fe7e6	Fix SRL16/32 techmap off-by-one	2019-02-28 13:56:00 -08:00
Eddie Hung	fe4d6898de	synth_xilinx to call shregmap with enable support	2019-02-28 11:17:13 -08:00
Eddie Hung	68f38f2ee0	synth_xilinx to use shregmap with -params too	2019-02-28 10:21:05 -08:00
Eddie Hung	c29f0c5048	Add techmap rule for $__SHREG_DFF_P_ to SRL16/32	2019-02-28 09:31:24 -08:00