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Author	SHA1	Message	Date
Clifford Wolf	c83b990458	Changed the AST genWidthRTLIL subst interface to use a std::map	2014-08-14 23:02:07 +02:00
Clifford Wolf	2f44d8ccf8	Added sig.{replace,remove,extract} variants for std::{map,set} pattern	2014-08-14 22:32:18 +02:00
Clifford Wolf	6d56172c0d	Fixed line numbers when using here-doc macros	2014-08-14 22:26:30 +02:00
Clifford Wolf	85e3cc12ac	Fixed handling of task outputs	2014-08-14 22:26:10 +02:00
Clifford Wolf	5602cbde9f	Simplified $__arraymul techmap rule	2014-08-14 20:53:21 +02:00
Clifford Wolf	1bf7a18fec	Added module->ports	2014-08-14 16:22:52 +02:00
Clifford Wolf	746aac540b	Refactoring of CellType class	2014-08-14 15:46:51 +02:00
Clifford Wolf	13f2f36884	RIP $safe_pmux	2014-08-14 11:39:46 +02:00
Clifford Wolf	28cf48e31f	Some improvements in FSM mapping and recoding	2014-08-14 11:22:45 +02:00
Clifford Wolf	996c06f64d	Added "abc -D" for setting delay target	2014-08-14 11:05:25 +02:00
Clifford Wolf	a878095b46	Updated ABC to 4935c2b946de	2014-08-14 10:19:12 +02:00
Clifford Wolf	7e758d5fbb	Added techmap support for actual lookahead carry unit	2014-08-13 18:40:57 +02:00
Clifford Wolf	9a065509ac	Preparations for lookahead ALU support in techmap.v	2014-08-13 16:36:30 +02:00
Clifford Wolf	28bc7aeb93	Filter ANSI escape sequences from ABC output	2014-08-13 13:40:29 +02:00
Clifford Wolf	c27120fcbc	New interface for $__alu in techmap.v	2014-08-13 13:04:28 +02:00
Clifford Wolf	f53984795d	Added support for non-standard """ macro bodies	2014-08-13 13:03:38 +02:00
Clifford Wolf	9d353fc543	Fixed handling of constant-true branches in proc_clean	2014-08-12 17:35:22 +02:00
Clifford Wolf	1dd8252169	Added test_verific mode to tests/fsm/generate.py	2014-08-12 15:43:30 +02:00
Clifford Wolf	e5ac8fdf2b	Fixed SigBit(RTLIL::Wire *wire) constructor	2014-08-12 15:39:48 +02:00
Clifford Wolf	593264e9ed	Fixed building verific bindings	2014-08-12 15:21:06 +02:00
Clifford Wolf	cad98bcd89	Added multi-dim memory test (requires iverilog git head)	2014-08-12 10:37:47 +02:00
Clifford Wolf	5215723c64	Another build fix by americanrouter (via reddit)	2014-08-11 15:55:41 +02:00
Clifford Wolf	788bd02f97	Fixed FSM mapping for multiple reset-like signals	2014-08-10 12:04:02 +02:00
Clifford Wolf	9d4362990f	Fixed "share" for complex scenarios with never-active cells	2014-08-09 17:07:20 +02:00
Clifford Wolf	b9811d5aff	Do not share any $reduce_* cells (its complicated and not worth it anyways)	2014-08-09 15:40:25 +02:00
Clifford Wolf	2faef89738	Some improvements in fsm_opt and fsm_map for FSM with unreachable states	2014-08-09 14:49:51 +02:00
Clifford Wolf	51aa5544fb	Improved FSM tests	2014-08-08 15:08:11 +02:00
Clifford Wolf	58ac605470	Another fsm_extract bugfix	2014-08-08 14:56:04 +02:00
Clifford Wolf	7067c43ec0	Fixed "fsm -export"	2014-08-08 14:56:03 +02:00
Clifford Wolf	cb6ca08a53	Fixed sharing of reduce operator	2014-08-08 14:24:09 +02:00
Clifford Wolf	7c94024fc3	Fixed fsm_extract for wreduced muxes	2014-08-08 13:47:20 +02:00
Clifford Wolf	c07774b0b6	Added FSM test bench	2014-08-08 13:12:18 +02:00
Clifford Wolf	622ebab671	Added "sat -prove-skip"	2014-08-08 13:11:54 +02:00
Clifford Wolf	0b8b8d41eb	Fixed build with gcc-4.6	2014-08-07 22:37:01 +02:00
Clifford Wolf	c55eb8f8a6	Use "-keepdc" in "miter -equiv -flatten"	2014-08-07 16:42:35 +02:00
Clifford Wolf	2dc3333734	Also allow "module foobar(input foo, output bar, ...);" syntax	2014-08-07 16:41:27 +02:00
Clifford Wolf	312ee00c9e	Added adff2dff.v (for techmap -share_map)	2014-08-07 16:14:38 +02:00
Clifford Wolf	d259abbda2	Added AST_MULTIRANGE (arrays with more than 1 dimension)	2014-08-06 15:52:54 +02:00
Clifford Wolf	b4f10e342c	Various improvements in memory_dff pass	2014-08-06 14:31:38 +02:00
Clifford Wolf	2501abe1ee	Various fixes and improvements in wreduce pass	2014-08-05 19:01:41 +02:00
Clifford Wolf	5b3dc07b9a	Removed old "constmap" from wreduce code	2014-08-05 16:53:53 +02:00
Clifford Wolf	523df73145	Added support for truncating of wires to wreduce pass	2014-08-05 14:47:03 +02:00
Clifford Wolf	d3b1a29708	Cleanups and improvements in wreduce pass	2014-08-05 13:11:04 +02:00
Clifford Wolf	1c182cedb7	Added mux support to wreduce command	2014-08-05 12:49:53 +02:00
Clifford Wolf	91dd87e60b	Improved scope resolution of local regs in Verilog+AST frontend	2014-08-05 12:15:53 +02:00
Clifford Wolf	0129d41efa	Fixed AST handling of variables declared inside a functions main block	2014-08-05 08:35:51 +02:00
Clifford Wolf	0bb6942218	Added "show -signed"	2014-08-04 15:40:08 +02:00
Clifford Wolf	b5a3419ac2	Added support for non-standard "module mod_name(...);" syntax	2014-08-04 15:40:07 +02:00
Clifford Wolf	ebbbe7fc83	Added RTLIL::IdString::in(...)	2014-08-04 15:40:07 +02:00
Clifford Wolf	c7f99be3be	Fixed "share" for memory read ports	2014-08-03 20:22:33 +02:00