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Author	SHA1	Message	Date
Emil J. Tywoniak	c7a8fe1c79	rtlil, patch: update signorm index and driver fields when committing Cell from Patch to Design	2026-07-17 23:48:06 +02:00
Emil J. Tywoniak	b95565a8d9	fixup! patch: working multi-cell signorm invariant	2026-07-17 23:48:06 +02:00
Emil J. Tywoniak	07d5115135	patch: source transfer	2026-07-17 23:48:06 +02:00
Emil J. Tywoniak	71f7f586aa	patch: working multi-cell signorm invariant	2026-07-17 23:48:06 +02:00
Emil J. Tywoniak	e331300c58	patch: fix patch mixins	2026-07-17 23:48:00 +02:00
Emil J. Tywoniak	2c1d114cb1	patch: WIP multicell patch test	2026-07-17 23:48:00 +02:00
Emil J. Tywoniak	8818cade7a	patch: wires	2026-07-17 23:48:00 +02:00
Emil J. Tywoniak	9f0c1843d3	patch: signorm, move	2026-07-17 23:48:00 +02:00
Emil J. Tywoniak	a00631595f	patch: unique heap	2026-07-17 23:48:00 +02:00
Emil J. Tywoniak	277b6f47dc	rtlil: add CellAdderMixin for shared Cell adder interface between Module and Patch	2026-07-17 23:48:00 +02:00
Emil J. Tywoniak	fc07fd9332	patch: GC comment	2026-07-17 23:47:35 +02:00
Emil J. Tywoniak	240dda9186	test_patch total basics	2026-07-17 23:47:35 +02:00
Emil J. Tywoniak	62cd00aeeb	rtlil: allow friends to use Wire constructors with a factory token pattern	2026-07-17 23:47:08 +02:00
Emil J. Tywoniak	20b0a9934b	rtlil: allow friends to use Cell constructors with a factory token pattern	2026-07-17 23:47:08 +02:00
Emil J. Tywoniak	77dd01edfc	patcher: start	2026-07-17 23:47:08 +02:00
Emil J. Tywoniak	0ff91a58d0	Revert "tests: use memory -bram-register in tests/bram" ... This reverts commit 24488a7011474080bcb99a91d38ae27b2c2d813c.	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	e21e48397e	tests: use memory -bram-register in tests/bram	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	d19258cd51	fixup! tests: signorm fix	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	9eafc15df7	tests: signorm fix	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	abebf4f2db	signorm: safer indexing if broken invariant	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	628cb4f4ca	check: check bufnorm too	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	9153c11b56	check: check signorm indices and wires	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	f2e5bcb86a	rtlil: publish signorm fanout	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	c9fb05efd6	opt_merge: newcelltypes	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	6336c0a602	opt_merge: factor out hashing code across incremental and parallel	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	a582aceaca	opt_expr: replace invert_map with signorm traversal	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	3010c0fc31	signorm: add timers	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	fb06c1add5	rtlil_bufnorm: fix setup_driven_wires constant handling on unknown port direction	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	061cec3166	check: fix memory bug in $connect	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	25e7118e4a	memory_bram: create blackboxes	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	8042d0dc77	Revert "intel: register bram celltypes" ... This reverts commit 16785a7f75af3a9d7be9f6450edbb927ce873d4a.	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	eaa67e8d36	Revert "tests: use memory -bram-register in tests/bram" ... This reverts commit 24488a7011474080bcb99a91d38ae27b2c2d813c.	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	76d8b2c2ea	Revert "memory: add -bram-register" ... This reverts commit 2bc6ea7f37f5c239491e83a3a8672af8954550ab.	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	6f09e55c95	Revert "memory_bram: add -register" ... This reverts commit b4b5093a14e5dceded852c644e70bf6ff447bba3.	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	1f745fb781	intel_alm: loosen tests	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	7cad14da7d	gowin: loosen tests	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	c8208db681	flatten: disable signorm	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	cc1bd1d4f1	ecp5: loosen tests	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	3de496e0c4	nexus: loosen tests	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	e313678594	xilinx_dsp: signorm compatibility	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	2291084045	pmgen: hold sigmap pointer instead of owning it	2026-07-17 23:38:01 +02:00
Emil J. Tywoniak	92475ecf62	equiv_miter: don't copy $input_port	2026-07-17 23:33:03 +02:00
Emil J. Tywoniak	83fa720157	rtlil_bufnorm: more xlog	2026-07-17 23:33:03 +02:00
Emil J. Tywoniak	15bd3bcfad	design: properly switch signorm mode when restoring saved designs	2026-07-17 23:33:03 +02:00
Emil J. Tywoniak	52ae92380d	equiv_make: don't copy $input_port	2026-07-17 23:33:03 +02:00
Emil J. Tywoniak	360527af1a	rtlil: fix cloneInto in signorm	2026-07-17 23:33:03 +02:00
Emil J. Tywoniak	2fc93aa711	rtlil: sigNormalize Module when added to Design in signorm mode	2026-07-17 23:33:03 +02:00
Emil J. Tywoniak	f7149450b4	rtlil_bufnorm: more xlog	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	1b19859e84	intel: register bram celltypes	2026-07-17 23:33:02 +02:00
Emil J. Tywoniak	c40974ee59	rtlil_bufnorm: ignore timing info harder	2026-07-17 23:33:02 +02:00