Marcin Kościelnicki
c6d5b97b98
review fixes
2019-08-13 00:35:54 +00:00
Marcin Kościelnicki
f4c62f33ac
Add clock buffer insertion pass, improve iopadmap.
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A few new attributes are defined for use in cell libraries:
- iopad_external_pin: marks PAD cell's external-facing pin. Pad
insertion will be skipped for ports that are already connected
to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
Clock buffer insertion will be skipped for nets that are already
driven by such a pin.
All three are module attributes that should be set to a comma-separeted
list of pin names.
Clock buffer insertion itself works as follows:
1. All cell ports, starting from bottom up, can be marked as clock sinks
(requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
also connected to a clock sink port in a contained cell, a clock
buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
connected to clock sinks, optionally with a special kind of input
PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
attribute is set on it.
2019-08-13 00:16:38 +02:00
Clifford Wolf
f54bf1631f
Merge pull request #1258 from YosysHQ/eddie/cleanup
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Cleanup a few barnacles across codebase
2019-08-10 09:52:14 +02:00
Clifford Wolf
6d0be8d206
Disable NMUX, AOI3, OAI3, AOI4, OAI4 in ABC default gate lib, add "abc -g all", fixes #1273
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-09 19:17:59 +02:00
Eddie Hung
6d77236f38
substr() -> compare()
2019-08-07 12:20:08 -07:00
Eddie Hung
7164996921
RTLIL::S{0,1} -> State::S{0,1}
2019-08-07 11:12:38 -07:00
Eddie Hung
e6d5147214
Merge remote-tracking branch 'origin/master' into eddie/cleanup
2019-08-07 11:11:50 -07:00
Eddie Hung
48d0f99406
stoi -> atoi
2019-08-07 11:09:17 -07:00
Eddie Hung
58e512ab70
Add comment
2019-08-07 09:54:27 -07:00
Eddie Hung
f20acbc813
Revert "Add TODO"
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This reverts commit 6068a6bf0d91e3ab9a5eaa33894a816f1560f99a.
2019-08-07 09:54:27 -07:00
Eddie Hung
789585a744
Add TODO
2019-08-07 09:54:27 -07:00
Eddie Hung
8a8c1d7857
Compute box_lookup just once
2019-08-07 09:54:27 -07:00
Eddie Hung
c11ad24fd7
Use std::stoi instead of atoi(<str>.c_str())
2019-08-06 16:45:48 -07:00
Eddie Hung
046e1a5214
Use State::S{0,1}
2019-08-06 16:22:47 -07:00
Eddie Hung
3486235338
Make liberal use of IdString.in()
2019-08-06 16:18:18 -07:00
Clifford Wolf
100c377451
Redesign of cell cost API
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-07 01:12:14 +02:00
Clifford Wolf
023086bd46
Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-06 04:47:55 +02:00
Clifford Wolf
0917a5cf72
Merge pull request #1238 from mmicko/vsbuild_fix
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Visual Studio build fix
2019-08-02 17:07:39 +02:00
Miodrag Milanovic
28b7053a01
Fix formatting for msys2 mingw build using GetSize
2019-08-01 17:27:34 +02:00
Miodrag Milanovic
35d28de478
Visual Studio build fix
2019-07-31 09:10:24 +02:00
Eddie Hung
5939b5d636
Merge pull request #1188 from YosysHQ/eddie/abc9_push_inverters
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abc9: push inverters driving box inputs (comb outputs) through $lut soft logic
2019-07-16 08:53:47 -07:00
Eddie Hung
ba8ccbdea8
Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fix
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abc9/ice40: encapsulate SB_CARRY+SB_LUT4 into one box
2019-07-16 08:52:14 -07:00
Miodrag Milanovic
2b469e82a7
Fix check logic in extract_fa
2019-07-16 10:35:18 +02:00
Eddie Hung
9b91d815b5
If ConstEval fails do not log_abort() but return gracefully
2019-07-13 04:13:57 -07:00
Eddie Hung
fb062c3426
Add comment
2019-07-13 00:52:21 -07:00
Eddie Hung
e9bdc86c0e
duplicate -> clone
2019-07-12 19:33:02 -07:00
Eddie Hung
be0cb7f4b8
More cleanup
2019-07-12 19:30:18 -07:00
Eddie Hung
7d583f9e57
Cleanup
2019-07-12 19:30:18 -07:00
Eddie Hung
83f23a24a8
Cleanup
2019-07-12 19:30:18 -07:00
Eddie Hung
1adbfb5533
Cleanup
2019-07-12 19:30:18 -07:00
Eddie Hung
39a7c7c54c
More cleanup
2019-07-12 19:30:18 -07:00
Eddie Hung
91c07be196
Cleanup
2019-07-12 19:30:18 -07:00
Eddie Hung
399e1ec870
Cleanup
2019-07-12 19:30:18 -07:00
Eddie Hung
58dbb28fd3
Cleanup
2019-07-12 19:30:18 -07:00
Eddie Hung
7dc15bdd2d
Do not double count cells in abc
2019-07-12 08:22:26 -07:00
Eddie Hung
c0abd18799
Enable &mfs for abc9, even if it only currently works for ice40
2019-07-11 08:49:06 -07:00
whitequark
ea447220da
attrmap: also consider process, switch and case attributes.
2019-07-10 12:30:53 +00:00
Eddie Hung
c2db70f41e
Increment _TECHMAP_BITS_CONNMAP_ by one since counting from zero
2019-07-09 12:14:00 -07:00
Eddie Hung
b5072256f2
Update muxcover doc as per @ZirconiumX
2019-07-08 12:50:59 -07:00
Eddie Hung
3681162c8d
atoi -> stoi
2019-07-08 11:00:06 -07:00
Eddie Hung
a34c5612e7
Add muxcover -mux2=cost option
2019-07-08 10:59:12 -07:00
Gabriel L. Somlo
8cb3655ecd
Make abc9 pass aware of optional ABCEXTERNAL override
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Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-06-28 14:56:16 -04:00
Eddie Hung
4a2a93aa06
Fix spacing
2019-06-28 11:10:36 -07:00
Eddie Hung
a625854ac5
Do not use Module::remove() iterator version
2019-06-27 15:29:20 -07:00
Eddie Hung
137c91d9a9
Remove &retime when abc9 -fast
2019-06-27 15:17:39 -07:00
Eddie Hung
6bf73e3546
Cleanup abc9.cc
2019-06-27 15:15:56 -07:00
Eddie Hung
6c256b8cda
Merge origin/master
2019-06-27 11:20:15 -07:00
Eddie Hung
c226af3f56
Fix spacing
2019-06-26 20:03:34 -07:00
Eddie Hung
26efd6f0a9
Support more than one port in the abc_scc_break attr
2019-06-26 19:57:54 -07:00
Eddie Hung
d2fed0a7f1
nullptr check
2019-06-25 06:06:32 -07:00
