Miodrag Milanovic
d5de2a0cdb
Make it work on all
2021-11-05 10:51:58 +01:00
Miodrag Milanovic
cbb6887ac8
Correct way of setting maybe_unsused on labels
2021-11-05 10:36:15 +01:00
Miodrag Milanovic
051b234df6
Add missing changelog item
2021-11-05 10:08:50 +01:00
Miodrag Milanovic
598f51c6a1
Update command reference
2021-11-05 10:04:15 +01:00
Miodrag Milanović
5a5244a12e
Merge pull request #3067 from YosysHQ/aki/ci_update
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Update the Linux and macOS CI jobs
2021-11-05 09:58:35 +01:00
Miodrag Milanovic
d67eb0eb1c
Removed semicolon from macro
2021-11-05 09:57:37 +01:00
github-actions[bot]
11e58d5415
Bump version
2021-11-03 00:52:24 +00:00
Marcelina Kościelnicka
f346868ccc
flatten: Keep sigmap around between flatten_cell invocations.
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Fixes #3064 .
2021-11-02 13:18:15 +01:00
github-actions[bot]
9cb5092ad1
Bump version
2021-11-02 00:56:31 +00:00
Claire Xen
5b834d3aff
Merge pull request #3068 from YosysHQ/claire/verific_cfg
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Add "verific -cfg" command
2021-11-01 12:53:47 +01:00
Claire Xenia Wolf
2ea757da51
Add "verific -cfg" command
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-11-01 10:41:51 +01:00
github-actions[bot]
97fce665c7
Bump version
2021-11-01 01:05:04 +00:00
Aki Van Ness
e1cfd37384
ci: removed the old test.yml workflow, as it was replaced by test-linux.yml and test-macos.yml
2021-10-31 20:07:43 -04:00
Aki Van Ness
1e7ba922e5
ci: expanded the macOS tests suite to cover more compilers and C++ versions
2021-10-31 20:07:43 -04:00
Aki Van Ness
ff31af6d72
ci: expanded the Linux test suite to cover more compilers and C++ versions
2021-10-31 20:07:43 -04:00
Aki Van Ness
ad81cff823
Changed the Makefile to have an explicit CXXSTD parameter which allows for the setting of other C++ standards, the default is c++11
2021-10-31 20:07:30 -04:00
Claire Xen
dd06d23649
Merge pull request #3066 from YosysHQ/claire/verific_gclk
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Fix verific gclk handling for async-load FFs
2021-10-31 18:04:54 +01:00
Claire Xenia Wolf
83118bfb9e
Fix verific gclk handling for async-load FFs
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-10-31 17:12:29 +01:00
github-actions[bot]
dcb7096b5a
Bump version
2021-10-30 00:51:07 +00:00
Miodrag Milanovic
c0edfa8788
Add missing items in CHANGELOG
2021-10-29 13:31:41 +02:00
Miodrag Milanovic
55f07fe56f
Update command reference part of manual
2021-10-29 13:10:50 +02:00
github-actions[bot]
5f00bf2d7d
Bump version
2021-10-28 00:52:35 +00:00
Miodrag Milanović
19c2d6e15d
Merge pull request #3063 from YosysHQ/micko/verific_aldff
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Enable async load dff emit by default in Verific
2021-10-27 17:20:31 +02:00
Marcelina Kościelnicka
e14302a3ea
ecp5: Add support for mapping aldff.
2021-10-27 16:18:05 +02:00
Miodrag Milanovic
f7cc388bb5
Enable async load dff emit by default in Verific
2021-10-27 15:56:56 +02:00
Miodrag Milanovic
32673edfea
Revert "Compile option for enabling async load verific support"
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This reverts commit b8624ad2ae
2021-10-27 15:55:43 +02:00
Marcelina Kościelnicka
8d881826eb
proc_dff: Emit $aldff.
2021-10-27 14:14:24 +02:00
Marcelina Kościelnicka
0b31cb598e
dfflegalize: Add tests for aldff lowering.
2021-10-27 14:14:01 +02:00
Marcelina Kościelnicka
54c79af64f
dfflegalize: Add tests targetting aldff.
2021-10-27 14:14:01 +02:00
Marcelina Kościelnicka
0a0df8d38c
dfflegalize: Refactor, add aldff support.
2021-10-27 14:14:01 +02:00
github-actions[bot]
bdf153d06c
Bump version
2021-10-27 00:51:44 +00:00
Zachary Snow
e833c6a418
verilog: use derived module info to elaborate cell connections
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- Attempt to lookup a derived module if it potentially contains a port
connection with elaboration ambiguities
- Mark the cell if module has not yet been derived
- This can be extended to implement automatic hierarchical port
connections in a future change
2021-10-25 18:25:50 -07:00
Rupert Swarbrick
bd16d01c0e
Split out logic for reprocessing an AstModule
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This will enable other features to use same core logic for replacing an
existing AstModule with a newly elaborated version.
2021-10-25 18:25:50 -07:00
github-actions[bot]
ee230f2bb9
Bump version
2021-10-26 00:51:59 +00:00
Miodrag Milanovic
b8624ad2ae
Compile option for enabling async load verific support
2021-10-25 09:04:43 +02:00
github-actions[bot]
52ba31b1c0
Bump version
2021-10-22 01:00:39 +00:00
Marcelina Kościelnicka
5cebf6a8ef
Change implicit conversions from bool to Sig* to explicit.
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Also fixes some completely broken code in extract_reduce.
2021-10-21 20:20:31 +02:00
Claire Xen
51d42cc917
Merge pull request #3057 from YosysHQ/claire/verific_latches
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Initial Verific impoter support for {PRIM,WIDE_OPER}_DLATCH{,RS}
2021-10-21 13:00:53 +02:00
Claire Xenia Wolf
90b440f870
Fix verific.cc PRIM_DLATCH handling
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-10-21 12:13:35 +02:00
Claire Xenia Wolf
16a177560f
Initial Verific impoter support for {PRIM,WIDE_OPER}_DLATCH{,RS}
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-10-21 05:42:47 +02:00
Marcelina Kościelnicka
e64456f920
extract_reduce: Refactor and fix input signal construction.
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Fixes #3047 .
2021-10-21 04:10:01 +02:00
github-actions[bot]
a0e9d9fef9
Bump version
2021-10-21 00:59:29 +00:00
Miodrag Milanovic
bf79ff5927
If verific have vhdl lib it is required by other libs
2021-10-20 13:08:08 +02:00
Miodrag Milanovic
150ce305f9
Forgot to remove from main list
2021-10-20 12:37:22 +02:00
Miodrag Milanovic
17269ae59b
Option to disable verific VHDL support
2021-10-20 10:02:58 +02:00
github-actions[bot]
69b2b13ddd
Bump version
2021-10-20 00:56:49 +00:00
Claire Xenia Wolf
fe9689c136
Fixed Verific parser error in ice40 cell library
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non-net output port 'Q' cannot be initialized at declaration in SystemVerilog mode
2021-10-19 12:33:18 +02:00
Miodrag Milanović
affed103e0
Merge pull request #3045 from galibert/master
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CycloneV: Add (passthrough) support for cyclonev_hps_interface_mpu_general_purpose
2021-10-19 11:23:57 +02:00
Claire Xenia Wolf
83887495b8
Fixes in vcdcd.pl for newer Perl versions
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-10-19 10:56:43 +02:00
github-actions[bot]
a15b01a777
Bump version
2021-10-18 00:56:23 +00:00
