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Miodrag Milanovic 2021-10-20 12:37:22 +02:00
parent 17269ae59b
commit 150ce305f9
1 changed files with 1 additions and 1 deletions
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Makefile
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@ -500,7 +500,7 @@ endif
ifeq ($(ENABLE_VERIFIC),1)
VERIFIC_DIR ?= /usr/local/src/verific_lib
VERIFIC_COMPONENTS ?= verilog vhdl database util containers hier_tree
VERIFIC_COMPONENTS ?= verilog database util containers hier_tree
ifneq ($(DISABLE_VERIFIC_VHDL),1)
VERIFIC_COMPONENTS += vhdl
CXXFLAGS += -DVERIFIC_VHDL_SUPPORT