Claire Wolf
47228feb77
Merge pull request #1708 from rqou/coolrunner2-buf-fix
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coolrunner2: Separate and improve buffer cell insertion pass
2020-02-27 19:03:59 +01:00
Piotr Binkowski
62ab100c61
xilinx: mark IOBUFDSE3 IOB pin as external
2020-02-27 13:15:57 +01:00
Miodrag Milanović
036c46de1e
Merge pull request #1705 from YosysHQ/logger_pass
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Logger pass
2020-02-26 13:32:49 +01:00
Miodrag Milanovic
80656ad178
Remove tests for now
2020-02-26 09:49:41 +01:00
Alberto Gonzalez
f80fe8dc22
Change attribute search value to specify precise location instead of simple line number.
2020-02-24 02:41:08 +00:00
Alberto Gonzalez
2c2f092c90
Change attribute search value to specify precise location instead of simple line number.
2020-02-24 01:39:36 +00:00
Miodrag Milanovic
c1cee15d64
Add tests for logger pass
2020-02-23 10:56:39 +01:00
Miodrag Milanovic
1c569fe06a
Remove duplicate warning detection
2020-02-23 10:56:27 +01:00
Miodrag Milanovic
48eed2860c
Fix line endings
2020-02-23 10:05:21 +01:00
Alberto Gonzalez
f0afd65035
Closes #1717 . Add more precise Verilog source location information to AST and RTLIL nodes.
2020-02-23 07:22:26 +00:00
Eddie Hung
6edca05793
Merge pull request #1715 from boqwxp/master
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Closes #1714 . Fix make failure when NDEBUG=1.
2020-02-22 11:29:22 -08:00
Marcus Comstedt
48a9b4f616
ecp5: Add missing parameter to \$__ECP5_PDPW16KD
2020-02-22 15:51:25 +01:00
Miodrag Milanovic
010d651450
Update explanation for expect-no-warnings
2020-02-22 10:53:23 +01:00
Miodrag Milanovic
d079ab9d19
Handle expect no warnings together with expected
2020-02-22 10:52:46 +01:00
Miodrag Milanovic
596bb2d443
Check other regex parameters
2020-02-22 10:31:56 +01:00
Alberto Gonzalez
750e7a9a54
Closes #1714 . Fix make failure when NDEBUG=1.
2020-02-22 06:29:11 +00:00
Eddie Hung
760096e8d2
Merge pull request #1703 from YosysHQ/eddie/specify_improve
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Improve specify parser
2020-02-21 09:15:17 -08:00
Claire Wolf
cd044a2bb6
Merge pull request #1642 from jjj11x/jjj11x/sv-enum
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Enum support
2020-02-20 18:17:25 +01:00
Miodrag Milanovic
419e67c170
check for regex errors
2020-02-20 11:41:37 +01:00
Eddie Hung
ea4bd161b6
verilog: add support for more delays than just rise/fall
2020-02-19 11:09:37 -08:00
Eddie Hung
1d401a7991
clean: ignore specify-s inside cells when determining whether to keep
2020-02-19 10:45:10 -08:00
Miodrag Milanovic
70db8e9200
Prevent double error message
2020-02-17 16:46:34 +01:00
Miodrag Milanovic
5641b0248f
Option to expect no warnings
2020-02-17 15:36:06 +01:00
Miodrag Milanovic
d8735b2913
Add to changelog
2020-02-17 15:08:35 +01:00
Miodrag Milanovic
be977cf7eb
No new error if already failing
2020-02-17 12:54:36 +01:00
R. Ou
13d0ff4a5f
coolrunner2: Use extract_counter to optimize counters
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This tends to make much more efficient pterm usage compared to just
throwing the problem at ABC
2020-02-17 03:09:40 -08:00
R. Ou
fec7dc5c9e
extract_counter: Implement extracting up counters
2020-02-17 03:08:52 -08:00
R. Ou
940bab6841
extract_counter: Add support for inverted clock enable
2020-02-17 03:08:52 -08:00
R. Ou
5fc180ed2d
extract_counter: Fix clock enable
2020-02-17 03:08:52 -08:00
R. Ou
12fa4a3121
extract_counter: Fix outputting count to module port
2020-02-17 03:08:52 -08:00
R. Ou
508f1ff6a1
extract_counter: Allow forbidding async reset
2020-02-17 03:08:52 -08:00
R. Ou
7b922c0d89
extract_counter: Refactor out extraction settings into struct
2020-02-17 03:08:52 -08:00
Jeff Wang
1c16311d10
update documentation for enums and typedefs
2020-02-17 04:42:55 -05:00
Jeff Wang
a31ba8e5d5
remove unnecessary blank line
2020-02-17 04:42:49 -05:00
Jeff Wang
d12ba42a74
add attributes for enumerated values in ilang
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- information also useful for strongly-typed enums (not implemented)
- resolves enum values in ilang part of #1594
- still need to output enums to VCD (or better yet FST) files
2020-02-17 04:42:42 -05:00
Jeff Wang
6320f2692b
separate out enum_item/param implementation when they should be different
2020-02-17 04:42:30 -05:00
R. Ou
6a0682f5a0
coolrunner2: Separate and improve buffer cell insertion pass
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The new pass will contain all of the logic for inserting "passthrough"
product term and XOR cells as appropriate for the architecture. For
example, this commit fixes connecting an input pin directly to another
output pin with no logic in between.
2020-02-16 20:25:46 -08:00
Marcin Kościelnicki
cd60f079d6
tests/aiger: Add missing .gitignore
2020-02-15 19:52:21 +01:00
Tim 'mithro' Ansell
b9dfdbbfee
show: Add -nobg argument.
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Makes yosys wait for the viewer command to finish before continuing.
2020-02-15 14:03:16 +01:00
Miodrag Milanović
2baa6d799e
Merge pull request #1706 from YosysHQ/mmicko/remove_executable_flag
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Remove executable flag from files
2020-02-15 11:15:35 +01:00
Miodrag Milanovic
cd5c177739
Remove executable flag from files
2020-02-15 10:36:44 +01:00
Miodrag Milanović
a7df492243
Add comment for macOS dependency install
2020-02-15 09:44:32 +01:00
Eddie Hung
f9f86fd758
Revert "abc9: fix abc9_arrival for flops"
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This reverts commit f7c0dbecee
2020-02-14 16:08:04 -08:00
Miodrag Milanovic
6b396e6455
remove whitespace
2020-02-14 13:12:05 +01:00
Miodrag Milanovic
31b7a9c312
Add expect option to logger command
2020-02-14 12:21:16 +01:00
Miodrag Milanović
c7af1b22ba
Merge pull request #1701 from nakengelhardt/rpc-test
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make rpc frontend unix socket test less fragile
2020-02-14 12:06:37 +01:00
Eddie Hung
d20c1dac73
verilog: ignore ranges too without -specify
2020-02-13 17:58:43 -08:00
Eddie Hung
0cf7598cd6
Merge pull request #1700 from YosysHQ/eddie/abc9_fixes
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Use (* abc9_init *) attribute, fix use of abc9_arrival for flops
2020-02-13 17:32:54 -08:00
Eddie Hung
8c4c546009
Merge pull request #1699 from YosysHQ/eddie/fix_iopad_init
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iopadmap: move \init attributes from outpad output to its input
2020-02-13 17:32:14 -08:00
Eddie Hung
3065d4092e
Fine tune #1699 tests
2020-02-13 15:14:58 -08:00
