3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-13 12:28:44 +00:00
Commit graph

2 commits

Author SHA1 Message Date
Miodrag Milanovic 0de328da8f Fixed Anlogic simulation model 2019-01-25 19:25:25 +01:00
Miodrag Milanovic 83bce9f59c Initial support for Anlogic FPGA 2018-12-01 18:28:54 +01:00