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Code Activity
6212 commits 103 branches 53 tags 51 MiB
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1921 commits

Author SHA1 Message Date
Eddie Hung
2ca83005fb abc9 to cope with multiple modules 2019-02-20 12:56:15 -08:00
Eddie Hung
d6b317b349 abc9 to use & syntax for -fast, and name fixes 2019-02-20 12:40:17 -08:00
Clifford Wolf
218e9051bb Add "synth_ice40 -dsp" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-20 16:42:27 +01:00
Clifford Wolf
246391200e Add FF support to wreduce 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-20 16:36:42 +01:00
Clifford Wolf
dca65d83a0 Detect and reject cases that do not map well to iCE40 DSPs (yet) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-20 11:18:19 +01:00
Eddie Hung
62e5ff9ba8 abc9 to cope with indexed wires when creating $lut from $_NOT_ 2019-02-19 16:06:03 -08:00
Jim Lawson
5c4a72c43e Fix normal (non-array) hierarchy -auto-top. 
Add simple test.
 2019-02-19 14:35:15 -08:00
Eddie Hung
8158bc3f99 abc9 to replace $_NOT_ with $lut 2019-02-19 12:30:20 -08:00
Clifford Wolf
5a853ed46c Add actual DSP inference to ice40_dsp pass 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-17 15:35:48 +01:00
Clifford Wolf
c06c062469 Merge branch 'master' of github.com:YosysHQ/yosys into pmgen 2019-02-17 12:10:19 +01:00
Eddie Hung
45d49d5d14 Get rid of debugging stuff in abc9 2019-02-16 22:25:22 -08:00
Eddie Hung
f853b2f3c1 abc9 to write_aiger with -O option, and ignore dummy outputs 2019-02-16 20:09:40 -08:00
Eddie Hung
d8c4d4e6c7 abc9 to handle comb loops, cope with constant outputs, disconnect using new wire 2019-02-16 13:47:38 -08:00
Eddie Hung
e7c7ab8fc0 expose command to not skip 'internal' wires beginning with '$' 2019-02-16 13:45:17 -08:00
Eddie Hung
d4545d415b abc9 to cope with non-wideports, count cells properly 2019-02-16 08:53:06 -08:00
Eddie Hung
f8d0134598 Move lookup inside if 2019-02-15 15:23:26 -08:00
Eddie Hung
a786ac4d53 Refactor 2019-02-15 13:00:13 -08:00
Eddie Hung
914546efd9 Cope with width != 1 when re-mapping cells 2019-02-15 12:55:52 -08:00
Eddie Hung
956ee545c5 abc9 to stitch results with CI/CO properly 2019-02-15 11:52:34 -08:00
Jim Lawson
5c504c5ae6 Define basic_cell_type() function and use it to derive the cell type for array references (instead of duplicating the code). 2019-02-15 11:31:37 -08:00
Eddie Hung
206f11dca3 Fix stitching 2019-02-13 17:04:23 -08:00
Eddie Hung
f0f5d8a5cc Merge remote-tracking branch 'origin/read_aiger' into xaig 2019-02-13 14:09:36 -08:00
Eddie Hung
06cf0555ee Merge https://github.com/YosysHQ/yosys into xaig 2019-02-13 14:08:31 -08:00
Eddie Hung
87f059adf7 Rip out some more stuff 2019-02-13 10:44:52 -08:00
Eddie Hung
045f7763ae Rip out unused functions in abc9 2019-02-12 16:25:22 -08:00
Eddie Hung
b3341b4abb WIP for ABC with aiger 2019-02-12 09:31:22 -08:00
Eddie Hung
c23e3f0751 Missing headers for Xcode? 2019-02-12 09:24:13 -08:00
Eddie Hung
5a0a5aae4f Compile abc9 2019-02-08 13:58:47 -08:00
Eddie Hung
e25a22015f Copy abc.cc to abc9.cc 2019-02-08 13:23:54 -08:00
David Shah
a4515712cb fsm_opt: Fix runtime error for FSMs without a reset state 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-07 10:35:36 +00:00
David Shah
58c22dae31 abc: Improved recovered netnames, also preserve src on nets with dress 
Signed-off-by: David Shah <davey1576@gmail.com>
 2019-02-06 22:23:13 +01:00
David Shah
8524a479b1 abc: Preserve naming through ABC using 'dress' command 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-06 22:23:13 +01:00
whitequark
58d059ccb7 proc_clean: fix critical typo. 2019-01-23 22:08:38 +00:00
whitequark
95b6c35882 proc_clean: fix fully def check to consider compare/signal length. 
Fixes #790.
 2019-01-18 23:22:19 +00:00
Clifford Wolf
8ddec5d882 Progress in pmgen 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-15 11:23:25 +01:00
Clifford Wolf
5216735210 Progress in pmgen, add pmgen README 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-15 11:23:25 +01:00
Clifford Wolf
55ac030382 Fix pmgen "reject" statement 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-15 11:23:25 +01:00
Clifford Wolf
d45379936b Progress in pmgen 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-15 11:23:25 +01:00
Clifford Wolf
1f8e76f993 Progress in pmgen 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-15 11:23:25 +01:00
Clifford Wolf
b9545aa0e1 Progress in pmgen 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-15 11:23:25 +01:00
Clifford Wolf
ad69c668ce Add mockup .pmg (pattern matcher generator) file 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-15 11:23:25 +01:00
whitequark
e792bd56b7 flowmap: clean up terminology. 
* "map": group gates into LUTs;
  * "pack": replace gates with LUTs.

This is important because we have FlowMap and DF-Map, and currently
our messages are ambiguous.

Also clean up some other log messages while we're at it.
 2019-01-08 02:05:06 +00:00
whitequark
211c26a4c9 flowmap: implement depth relaxation. 2019-01-08 01:13:05 +00:00
Clifford Wolf
8a63fc51d3 Bugfix in $memrd sharing 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-07 10:04:47 +01:00
Clifford Wolf
dbd51d7bda
Merge pull request #782 from whitequark/flowmap_dfs 
flowmap: construct a max-volume max-flow min-cut, not just any one
 2019-01-07 09:47:57 +01:00
Clifford Wolf
b5f6e786ea Switch "bugpoint" from system() to run_command() 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-07 09:45:21 +01:00
whitequark
a342d6db49 bugpoint: new pass. 
A typical use of `bugpoint` would involve a script with a pass under
test, e.g.:

    flowmap -relax -optarea 100

and would be invoked as:

    bugpoint -yosys ./yosys -script flowmap.ys -clean -cells

This replaces the current design with the minimal design that still
crashes the `flowmap.ys` script.

`bugpoint` can also be used to perform generic design minimization
using `select`, e.g. the following script:

    select i:* %x t:$_MUX_ %i -assert-max 0

would remove all parts of the design except for an unbroken path from
an input to an output port that goes through exactly one $_MUX_ cell.
(The condition is inverted.)
 2019-01-07 03:13:19 +00:00
whitequark
8b44198e23 flowmap: construct a max-volume max-flow min-cut, not just any one. 2019-01-06 19:51:37 +00:00
Scott Mansell
62c90c4e17 Rename cells based on the wires they drive. 2019-01-06 19:00:16 +13:00
whitequark
2fcc1ee72e flowmap: add -minlut option, to allow postprocessing with opt_lut. 2019-01-04 21:18:03 +00:00