612 commits

Author	SHA1	Message	Date
Clifford Wolf	5e39e6ece2	Correctly convert constants to RTLIL (fixed undef handling)	2014-02-15 15:42:10 +01:00
Clifford Wolf	45d2b6ffce	Be more conservative with new const-function code	2014-02-14 20:45:30 +01:00
Clifford Wolf	e8af3def7f	Added support for FOR loops in function calls in parameters	2014-02-14 20:33:22 +01:00
Clifford Wolf	534c1a5dd0	Created basic support for function calls in parameter values	2014-02-14 19:56:44 +01:00
Clifford Wolf	cd9e8741a7	Implemented read_verilog -defer	2014-02-13 13:59:13 +01:00
Clifford Wolf	f4f230d7cc	Fixed gcc compiler warnings with release build	2014-02-06 22:49:14 +01:00
Clifford Wolf	d267bcde4e	Fixed bug in sequential sat proofs and improved handling of asserts	2014-02-04 12:46:16 +01:00
Clifford Wolf	a6750b3753	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	2014-02-03 13:01:45 +01:00
Clifford Wolf	d06258f74f	Added constant size expression support of sized constants	2014-02-01 13:50:23 +01:00
Clifford Wolf	4df7e03ec9	Bugfix in name resolution with generate blocks	2014-01-30 15:01:28 +01:00
Clifford Wolf	375c4dddc1	Added read_verilog -icells option	2014-01-29 00:59:28 +01:00
Clifford Wolf	88fbdd4916	Fixed algorithmic complexity of AST simplification of long expressions	2014-01-20 20:25:20 +01:00
Clifford Wolf	1e67099b77	Added $assert cell	2014-01-19 14:03:40 +01:00
Clifford Wolf	9a1eb45c75	Added Verilog parser support for asserts	2014-01-19 04:18:22 +01:00
Clifford Wolf	a3d94bf888	Fixed typo in frontends/ast/simplify.cc	2014-01-12 21:04:42 +01:00
Clifford Wolf	fb2bf934dc	Added correct handling of $memwr priority	2014-01-03 00:22:17 +01:00
Clifford Wolf	364f277afb	Fixed a stupid access after delete bug	2013-12-29 20:18:22 +01:00
Clifford Wolf	369bf81a70	Added support for non-const === and !== (for miter circuits)	2013-12-27 14:20:15 +01:00
Clifford Wolf	ecc30255ba	Added proper === and !== support in constant expressions	2013-12-27 13:50:08 +01:00
Clifford Wolf	891e4b5b0d	Keep strings as strings in const ternary and concat	2013-12-05 13:26:17 +01:00
Clifford Wolf	e935bb6eda	Added const folding support for $signed and $unsigned	2013-12-05 13:09:41 +01:00
Clifford Wolf	5c39948ead	Added AstNode::mkconst_str API	2013-12-05 12:53:49 +01:00
Clifford Wolf	853538d78b	Fixed generate-for (and disabled double warning for auto-wire)	2013-12-04 21:33:00 +01:00
Clifford Wolf	3c220e0b32	Added support for $clog2 system function	2013-12-04 21:19:54 +01:00
Clifford Wolf	4a4a3fc337	Various improvements in support for generate statements	2013-12-04 21:06:54 +01:00
Clifford Wolf	f4b46ed31e	Replaced signed_parameters API with CONST_FLAG_SIGNED	2013-12-04 14:24:44 +01:00
Clifford Wolf	93a70959f3	Replaced RTLIL::Const::str with generic decoder method	2013-12-04 14:14:05 +01:00
Clifford Wolf	507c63d112	Added support for local regs in named blocks	2013-12-04 09:10:16 +01:00
Clifford Wolf	10aa08dca1	Fixed temp net name generation in rtlil process generator for abbreviated name matching	2013-11-28 21:47:08 +01:00
Clifford Wolf	0e52f3fa01	Added "src" attribute to processes	2013-11-28 17:37:50 +01:00
Clifford Wolf	8dafecd34d	Added module->avail_parameters (for advanced techmap features)	2013-11-24 20:29:07 +01:00
Clifford Wolf	7d9a90396d	Added verilog frontend -ignore_redef option	2013-11-24 19:57:42 +01:00
Clifford Wolf	019b301541	Early wire/reg/parameter width calculation in ast/simplify	2013-11-24 19:40:23 +01:00
Clifford Wolf	f71e27dbf1	Remove auto_wire framework (smarter than the verilog standard)	2013-11-24 17:29:11 +01:00
Clifford Wolf	609caa23b5	Implemented correct handling of signed module parameters	2013-11-24 17:17:21 +01:00
Clifford Wolf	295e352ba6	Renamed "placeholder" to "blackbox"	2013-11-22 15:01:12 +01:00
Clifford Wolf	95c94a02fc	Fixed async proc detection in mem2reg	2013-11-21 21:26:56 +01:00
Clifford Wolf	09471846c5	Major improvements in mem2reg and added "init" sync rules	2013-11-21 13:49:00 +01:00
Clifford Wolf	65ad556f3d	Another name resolution bugfix for generate blocks	2013-11-20 13:57:40 +01:00
Clifford Wolf	c4c299eb5a	Do not allow memory bit select on the left side of an assignment	2013-11-20 12:18:46 +01:00
Clifford Wolf	ac2be2d892	Fixed name resolution of local tasks and functions in generate block	2013-11-20 11:05:58 +01:00
Clifford Wolf	19dba2561e	Implemented part/bit select on memory read	2013-11-20 10:51:32 +01:00
Clifford Wolf	4f2edcf2f9	Fixed two bugs in mem2reg functionality in AST frontend	2013-11-18 19:55:12 +01:00
Clifford Wolf	79910a5547	Added dumping of attributes in AST frontend	2013-11-18 19:54:36 +01:00
Clifford Wolf	2a25e3bca3	Fixed parsing of default cases when not last case	2013-11-18 16:10:50 +01:00
Clifford Wolf	de03184150	Fixed mem2reg for reg usage outside always block	2013-11-18 12:35:41 +01:00
Clifford Wolf	e5b974fa2a	Cleanups and bugfixes in response to new internal cell checker	2013-11-11 00:39:45 +01:00
Clifford Wolf	378cc509cd	Call internal checker more often	2013-11-10 23:24:21 +01:00
Clifford Wolf	259cc1391e	More undef-propagation related fixes	2013-11-08 11:40:36 +01:00
Clifford Wolf	9f49d538e1	Fixed handling of different signedness in power operands	2013-11-08 11:06:11 +01:00