612 commits

Author	SHA1	Message	Date
Clifford Wolf	cc4f10883b	Renamed RTLIL::{Module,Cell}::connections to connections_	2014-07-26 11:58:03 +02:00
Clifford Wolf	2bec47a404	Use only module->addCell() and module->remove() to create and delete cells	2014-07-25 17:56:19 +02:00
Clifford Wolf	309d64d46a	Fixed two memory leaks in ast simplify	2014-07-25 13:24:10 +02:00
Clifford Wolf	6aa792c864	Replaced more old SigChunk programming patterns	2014-07-24 23:10:58 +02:00
Clifford Wolf	20a7965f61	Various small fixes (from gcc compiler warnings)	2014-07-23 20:45:27 +02:00
Clifford Wolf	c094c53de8	Removed RTLIL::SigSpec::optimize()	2014-07-23 20:32:28 +02:00
Clifford Wolf	115dd959d9	SigSpec refactoring: More cleanups of old SigSpec use pattern	2014-07-22 23:50:21 +02:00
Clifford Wolf	28b3fd05fa	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()	2014-07-22 20:58:44 +02:00
Clifford Wolf	7bffde6abd	SigSpec refactoring: change RTLIL::SigSpec::size() to be read-only	2014-07-22 20:39:38 +02:00
Clifford Wolf	4b4048bc5f	SigSpec refactoring: using the accessor functions everywhere	2014-07-22 20:39:37 +02:00
Clifford Wolf	a233762a81	SigSpec refactoring: renamed chunks and width to __chunks and __width	2014-07-22 20:39:37 +02:00
Clifford Wolf	9b183539af	Implemented dynamic bit-/part-select for memory writes	2014-07-17 16:49:23 +02:00
Clifford Wolf	5867f6bcdc	Added support for bit/part select to mem2reg rewriter	2014-07-17 13:49:32 +02:00
Clifford Wolf	6d69d4aaa8	Added support for constant bit- or part-select for memory writes	2014-07-17 13:13:21 +02:00
Clifford Wolf	543551b80a	changes in verilog frontend for new $mem/$memwr WR_EN interface	2014-07-16 12:49:50 +02:00
Clifford Wolf	55a1b8dbac	Fixed processing of initial values for block-local variables	2014-07-11 13:05:53 +02:00
Clifford Wolf	076182c34e	Fixed handling of mixed real/int ternary expressions	2014-06-25 10:05:36 +02:00
Clifford Wolf	4fc43d1932	More found_real-related fixes to AstNode::detectSignWidthWorker	2014-06-24 15:08:48 +02:00
Clifford Wolf	65b2e9c064	fixed signdness detection for expressions with reals	2014-06-21 21:41:13 +02:00
Clifford Wolf	80e4594695	Added AstNode::MEM2REG_FL_CMPLX_LHS	2014-06-17 21:39:25 +02:00
Clifford Wolf	798ff88855	Improved handling of relational op of real values	2014-06-17 12:47:51 +02:00
Clifford Wolf	6c17d4f242	Improved ternary support for real values	2014-06-16 15:12:24 +02:00
Clifford Wolf	82bbd2f077	Use undef (x/z vs. NaN) rules for real values from IEEE Std 1800-2012	2014-06-16 15:05:37 +02:00
Clifford Wolf	5bfe865cec	Added found_real feature to AstNode::detectSignWidth	2014-06-16 15:00:57 +02:00
Clifford Wolf	4d1df128fa	Improved AstNode::realAsConst for large numbers	2014-06-15 09:27:09 +02:00
Clifford Wolf	48dc6ab98d	Improved AstNode::asReal for large integers	2014-06-15 08:38:31 +02:00
Clifford Wolf	149fe83a8d	improved (fixed) conversion of real values to bit vectors	2014-06-14 21:00:51 +02:00
Clifford Wolf	d5765b5e14	Fixed relational operators for const real expressions	2014-06-14 19:33:58 +02:00
Clifford Wolf	f3b4a9dd24	Added support for math functions	2014-06-14 13:36:23 +02:00
Clifford Wolf	9bd7d5c468	Added handling of real-valued parameters/localparams	2014-06-14 12:00:47 +02:00
Clifford Wolf	fc7b6d172a	Implemented more real arithmetic	2014-06-14 11:27:05 +02:00
Clifford Wolf	442a8e2875	Implemented basic real arithmetic	2014-06-14 08:51:22 +02:00
Clifford Wolf	9dd16fa41c	Added real->int convertion in ast genrtlil	2014-06-14 07:44:19 +02:00
Clifford Wolf	7ef0da32cd	Added Verilog lexer and parser support for real values	2014-06-13 11:29:23 +02:00
Clifford Wolf	e275e8eef9	Add support for cell arrays	2014-06-07 11:48:50 +02:00
Clifford Wolf	0b1ce63a19	Added support for repeat stmt in const functions	2014-06-07 10:47:53 +02:00
Clifford Wolf	7c8a7b2131	further improved const function support	2014-06-07 00:02:05 +02:00
Clifford Wolf	76da2fe172	improved const function support	2014-06-06 22:55:02 +02:00
Clifford Wolf	5c10d2ee36	fix functions with no block (but single statement, loop, etc.)	2014-06-06 21:29:23 +02:00
Clifford Wolf	ab54ce17c8	improved ast simplify of const functions	2014-06-06 17:40:45 +02:00
Clifford Wolf	b5cd7a0179	added while and repeat support to verilog parser	2014-06-06 17:40:04 +02:00
Clifford Wolf	09805ee9ec	Include id2ast pointers when dumping AST	2014-03-05 19:56:31 +01:00
Clifford Wolf	d6a01fe412	Fixed merging of compatible wire decls in AST frontend	2014-03-05 19:55:58 +01:00
Clifford Wolf	de7bd12004	Bugfix in recursive AST simplification	2014-03-05 19:45:33 +01:00
Clifford Wolf	ae5032af84	Fixed bit-extending in $mux argument (use $bu0 instead of $pos)	2014-02-26 21:32:19 +01:00
Clifford Wolf	6bc94b7eb2	Don't blow up constants unneccessarily in Verilog frontend	2014-02-24 12:41:25 +01:00
Clifford Wolf	f8c9143b2b	Fixed bug in generation of undefs for $memwr MUXes	2014-02-22 17:08:00 +01:00
Clifford Wolf	4bd25edcd4	Cleanups in handling of read_verilog -defer and -icells	2014-02-20 19:12:32 +01:00
Clifford Wolf	02e6f2c5be	Added Verilog support for "`default_nettype none"	2014-02-17 14:28:52 +01:00
Clifford Wolf	7ac524e8e8	Improved support for constant functions	2014-02-16 13:16:38 +01:00