Philippe Sauter
cbdf9b2f9c
peepopt: handle empty src-attribute in shiftadd
2024-01-31 13:07:01 +01:00
github-actions[bot]
3bc83c6533
Bump version
2024-01-31 00:15:44 +00:00
hakan-demirli
8c731658c2
Merge branch 'YosysHQ:master' into master
2024-01-31 01:03:59 +03:00
hakan-demirli
039634d973
feat: mkdir with tree
2024-01-31 01:03:01 +03:00
Claire Xenia Wolf
4fa314c0bd
Add API to overwrite existing pass from plugin
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2024-01-30 17:51:11 +01:00
Miodrag Milanovic
db1de5fe5d
verific: add option to skip simplifying complex ports
2024-01-30 16:33:44 +01:00
Martin Povišer
3537976477
Merge pull request #4163 from QuantamHD/fix_write_verilog
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write_verilog: Making sure BUF cells are converted to expressions.
2024-01-30 10:58:42 +01:00
Philippe Sauter
7f8b6dd982
peepopt: delete unnecessary comment in shiftadd
2024-01-30 09:51:21 +01:00
Miodrag Milanović
b572e1af9f
Merge pull request #4171 from yrabbit/sdp-wre
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gowin: Fix SDP write enable port.
2024-01-30 08:49:50 +01:00
YRabbit
79c5a06673
gowin: Fix SDP write enable port.
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This primitive does not have a separate WRE port, so we regulate writing
using Clock Enable.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2024-01-30 17:06:59 +10:00
Ethan Mahintorabi
3076875fff
removing call to dump_attributes to remove possibility of generating invalid verilog
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Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
2024-01-30 00:56:07 +00:00
github-actions[bot]
112bcb0907
Bump version
2024-01-30 00:15:11 +00:00
N. Engelhardt
027cb31e9d
Merge pull request #4161 from YosysHQ/nak/add_sig_extract_asserts
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SigSpec/SigChunk::extract(): assert offset/length are not out of range
2024-01-29 16:11:01 +01:00
Martin Povišer
2f4dd9961c
Merge pull request #4162 from jix/sim-print-sampling
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sim: Bring $print trigger/sampling semantics in line with FFs
2024-01-29 15:39:46 +01:00
N. Engelhardt
a9fe85c2d0
Merge pull request #4141 from YosysHQ/small_build
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Make small build links, and support Verific small build
2024-01-29 15:17:39 +01:00
Jannis Harder
fd838a99ce
Merge pull request #4140 from jix/writer_aiger_sccs
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write_aiger: Detect and error out on combinational loops
2024-01-29 15:14:54 +01:00
N. Engelhardt
2282351172
Merge pull request #4118 from povik/fix-conn-on-wire-delete
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rtlil: Fix handling of connections on wire deletion
2024-01-29 15:08:48 +01:00
Martin Povišer
7afc0696e2
opt_clean: Assert an impossible path isn't taken
2024-01-29 11:26:44 +01:00
Martin Povišer
ec065186d3
opt_clean: Add commentary around wire cleaning, NFC
2024-01-29 11:26:44 +01:00
Martin Povišer
ea3dc7c1b4
rtlil: Add wire deletion test
2024-01-29 11:25:54 +01:00
Martin Povišer
c035289383
rtlil: Do not create dummy wires when deleting wires in connections
2024-01-29 11:25:54 +01:00
Martin Povišer
d6600fb1d5
rtlil: Fix handling of connections on wire deletion
2024-01-29 11:25:54 +01:00
github-actions[bot]
4585d60b8a
Bump version
2024-01-28 00:17:09 +00:00
Miodrag Milanović
887c90500a
Merge pull request #4166 from YosysHQ/update-workflows
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Update workflows to Node.js 20
2024-01-27 09:06:23 +01:00
Miodrag Milanović
54c5431cfc
Merge pull request #4167 from yrabbit/wip-byte-enable
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gowin: Change BYTE ENABLE handling.
2024-01-27 09:04:42 +01:00
YRabbit
a5fdf3f881
gowin: Change BYTE ENABLE handling.
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When inferring we allow writing to all bytes for now.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2024-01-27 17:19:49 +10:00
Krystine Sherwin
7e524e0588
Update workflows to Node.js 20
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Node.js 16 actions are deprecated. For more information see: https://github.blog/changelog/2023-09-22-github-actions-transitioning-from-node-16-to-node-20/ .
2024-01-27 11:20:48 +13:00
Philippe Sauter
68a9aa7c29
peepopt: handle offset too large in shiftadd
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If the offset is larger than the signal itself,
meaning the signal is completely shifted out,
it tried to extract a negative amount of bits from the old signal.
This RTL pattern is suspicious since it is a complicated way of
arriving at a constant value, so we warn the user.
2024-01-26 16:44:30 +01:00
Ethan Mahintorabi
33fe2e4613
fixes char* to string conversion issue
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Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
2024-01-25 17:39:18 +00:00
Ethan Mahintorabi
d2a04cca0e
write_verilog: Making sure BUF cells are converted to expressions.
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These were previously not being converted correctly leading to yosys
internal cells being written to my netlist.
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
2024-01-25 17:00:05 +00:00
Jannis Harder
7c818d30f7
sim: Bring $print trigger/sampling semantics in line with FFs
2024-01-25 16:21:03 +01:00
N. Engelhardt
efe4d6dbdc
SigSpec/SigChunk::extract(): assert offset/length are not out of range
2024-01-25 12:28:17 +01:00
github-actions[bot]
80511ced71
Bump version
2024-01-25 00:16:42 +00:00
Martin Povišer
6707db93b9
Merge pull request #4157 from whitequark/cxxrtl-fix-4144
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cxxrtl: fix typo in codegen for async set/clear
2024-01-24 18:48:45 +01:00
Martin Povišer
08fd47e970
Test roundtripping some processes to Verilog and back
2024-01-24 16:32:25 +00:00
Catherine
9cbfad2691
write_verilog: don't emit code with dangling else related to wrong condition.
2024-01-24 16:32:25 +00:00
Catherine
b841d1bcbe
cxxrtl: fix typo in codegen for async set/clear.
2024-01-24 16:30:01 +00:00
github-actions[bot]
3c3788ee28
Bump version
2024-01-24 00:16:36 +00:00
Gabriel Gouvine
c634d59c18
Issue a warning instead of a syntax error for blif delay constraints
2024-01-23 16:25:16 +00:00
Miodrag Milanovic
ddfd867d29
hardcode iverilog version so it works on forkes and in PRs
2024-01-23 17:22:56 +01:00
github-actions[bot]
2f9fcc2e50
Bump version
2024-01-23 00:16:43 +00:00
Miodrag Milanović
3123dac77a
Merge pull request #4148 from YosysHQ/set_iverilog
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Checkout specific iverilog version (can be master as well)
2024-01-22 18:29:36 +01:00
Miodrag Milanovic
cfcd0b5729
Checkout specific iverilog version (can be master as well)
2024-01-22 17:18:39 +01:00
Catherine
3d9e44d182
hierarchy: keep display statements, like formal assertions.
2024-01-22 10:09:22 +00:00
Martin Povišer
2c4cf2b4b8
Merge pull request #4147 from stong/fix-typo
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Fix typo in stat help
2024-01-22 10:52:01 +01:00
Stephen Tong
b3e7390c0e
Fix typo in stat help
2024-01-21 16:32:05 -05:00
github-actions[bot]
8649e30668
Bump version
2024-01-20 00:16:07 +00:00
Catherine
fc5ff7a265
cxxrtl: always lazily format print messages.
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This is mostly useful for collecting coverage for the future `$check`
cell, where, depending on the flavor, formatting a message may not be
wanted even for a failed assertion.
2024-01-19 18:55:23 +00:00
Miodrag Milanovic
b11449badb
Make small build links, and support verific small build
2024-01-19 16:30:35 +01:00
Catherine
b74d33d1b8
fmt: rename TIME to VLOG_TIME.
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The behavior of these format specifiers is highly specific to Verilog
(`$time` and `$realtime` are only defined relative to `$timescale`)
and may not fit other languages well, if at all. If they choose to use
it, it is now clear what they are opting into.
This commit also simplifies the CXXRTL code generation for these format
specifiers.
2024-01-19 15:12:05 +00:00
