414 commits

Author	SHA1	Message	Date
Clifford Wolf	c69c416d28	Added $bu0 cell (for easy correct $eq/$ne mapping)	2013-12-28 12:02:14 +01:00
Clifford Wolf	369bf81a70	Added support for non-const === and !== (for miter circuits)	2013-12-27 14:20:15 +01:00
Clifford Wolf	76f7c10cfc	Using simplemap mappers from techmap	2013-11-24 23:31:14 +01:00
Clifford Wolf	1afe6589df	Renamed stdcells_sim.v to simcells.v and fixed blackbox.v	2013-11-24 20:44:00 +01:00
Clifford Wolf	0c91f890c9	Install simlib in datdir	2013-11-19 23:05:46 +01:00
Clifford Wolf	e5b974fa2a	Cleanups and bugfixes in response to new internal cell checker	2013-11-11 00:39:45 +01:00
Clifford Wolf	404b46674b	Fixed techmap of $reduce_xnor with multi-bit outputs	2013-11-07 00:58:06 +01:00
Clifford Wolf	b41740060b	Fixed techmap of $gt and $ge with multi-bit outputs	2013-11-06 22:59:45 +01:00
Clifford Wolf	6fcbc79b5c	Improved width extension with regard to undef propagation	2013-11-06 21:05:11 +01:00
Clifford Wolf	0836a1f2ba	Bugfix in dffsr techmap rules	2013-10-18 13:24:44 +02:00
Clifford Wolf	8197169f8d	Added techmap rules for $sr, $dffsr and $dlatch	2013-10-18 12:29:21 +02:00
Clifford Wolf	e0f693cbb0	Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_	2013-10-18 12:13:34 +02:00
Clifford Wolf	5998c101a4	Added $sr, $dffsr and $dlatch cell types	2013-10-18 11:56:16 +02:00
Clifford Wolf	288ba9618a	Moved common techlib files to techlibs/common	2013-09-15 11:52:57 +02:00