Lofty
b8b47f7c6c
Revert "ice40, ecp5: enable ABC9 by default"
2023-11-03 14:52:52 +00:00
Lofty
32082477b5
ice40, ecp5: enable ABC9 by default
2023-11-03 08:52:54 +00:00
Lofty
294844137b
gowin: fix abc9 attributes and specify blocks
2023-10-04 00:16:10 +01:00
Martin Povišer
54be4aca90
Merge pull request #3924 from andyfox-rushc/master
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multpass -- create Booth Encoded multipliers for
2023-09-18 16:46:59 +02:00
Jannis Harder
78ff40d1b2
Run future as part of prep
2023-09-13 11:32:36 +02:00
Miodrag Milanovic
27ac912709
Support import of $future_ff
2023-09-13 11:32:36 +02:00
Miodrag Milanovic
54050a8c16
Basic support for tag primitives
2023-09-13 11:32:36 +02:00
andyfox-rushc
0fa412502c
mult -> booth in synth.cc, to turn on use synth -booth
2023-09-08 16:44:59 -07:00
andyfox-rushc
1d92ea8001
Support for turning on mult pass from generic synth command
2023-09-08 16:16:24 -07:00
Miodrag Milanovic
72bec94ef4
Add missing file for XO3D
2023-09-01 10:15:51 +02:00
Miodrag Milanovic
792cf8326e
defult nowidelut for xo2/3/3d
2023-08-29 10:08:55 +02:00
Miodrag Milanovic
b168ff99d0
fix generated blackboxes for ecp5
2023-08-28 16:26:26 +02:00
Miodrag Milanovic
0756285710
enable more primitives supported with nextpnr
2023-08-25 11:45:25 +02:00
Miodrag Milanovic
3b9ebfa672
Addressed code review comments
2023-08-25 11:10:20 +02:00
Miodrag Milanovic
541c1ab567
add script for blackbox extraction
2023-08-23 11:51:00 +02:00
Miodrag Milanovic
75fd706487
delete machxo2 since it is now supported in lattice
2023-08-23 10:54:17 +02:00
Miodrag Milanovic
e3c15f003e
Create synth_lattice
2023-08-23 10:53:21 +02:00
Miodrag Milanovic
a8809989c4
ecp5_gsr -> lattice_gsr, change opt_lut_ins to accept lattice as tech
2023-08-22 10:50:11 +02:00
Charlotte
f9d38253c5
ast: add PRIORITY to $print cells
2023-08-11 04:46:52 +02:00
Charlotte
4e94f62116
simlib: blackbox $print cell
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It's possible to `generate` the appropriate always blocks per the
triggers, but unlikely to be worth parsing the RTLIL \FORMAT parameter.
2023-08-11 04:46:52 +02:00
Patrick Urban
61387d78b7
gatemate: Prevent implicit declaration of ram_{we,en}
2023-06-05 19:08:44 +02:00
Patrick Urban
2004a9ff4a
gatemate: Add CC_FIFO_40K simulation model
2023-05-30 09:06:23 +02:00
Patrick Urban
c244a7161b
gatemate: Fix SDP read behavior
2023-05-30 09:05:43 +02:00
Lofty
fb7af093a8
intel_alm: re-enable 8x40-bit M10K support
2023-05-29 06:42:03 +01:00
Lofty
cac1bc6fbe
intel_alm: enable M10K initialisation
2023-05-25 18:56:34 +01:00
Lofty
00b0e850db
intel_alm: re-enable carry chains for ABC9
2023-05-25 18:28:10 +01:00
Miodrag Milanović
7aab324e85
Merge pull request #3737 from yrabbit/all-primitives-script
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gowin: Add all the primitives.
2023-05-09 11:13:51 +02:00
Ralf Fuest
30f1d10948
gowin: Fix X output of $alu techmap
2023-05-01 17:56:41 +02:00
YRabbit
a1dd794ff8
gowin: Add all the primitives.
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Use selected data (names, ports and parameters) from vendor file for
GW1N series primitives.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2023-04-22 17:10:53 +10:00
Miodrag Milanović
b377a39b73
Merge pull request #3727 from YosysHQ/micko/pll_bram
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MachXO2: Add PLL and EBR related primitives
2023-04-14 09:34:30 +02:00
gatecat
e56dad56c4
fabulous: Add support for LUT6s
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Signed-off-by: gatecat <gatecat@ds0.me>
2023-04-12 18:42:09 +02:00
YRabbit
f9a6c0fcbd
gowin: Add serialization/deserialization primitives
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Primitives are added to convert parallel signals to serial and vice versa.
IDES4, IDES8, IDES10, IDES16, IVIDEO, OSER4, OSER8, OSER10, OSER16, OVIDEO.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2023-04-12 09:59:57 +01:00
Miodrag Milanovic
ee3162c58d
Add PLL and EBR related primitives
2023-04-10 12:39:09 +02:00
gatecat
266f81816b
ecp5: Remove TRELLIS_SLICE and add TRELLIS_COMB model
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Signed-off-by: gatecat <gatecat@ds0.me>
2023-04-06 10:18:48 +01:00
Miodrag Milanovic
9e9fae1966
Add more DFF types
2023-04-06 09:10:14 +02:00
Miodrag Milanovic
d5a405d3b4
Added proper simulation model for CCU2D
2023-04-06 09:10:14 +02:00
Miodrag Milanovic
6e4c1675e7
Generate TRELLIS_DPR16X4 for lutram
2023-04-06 09:10:14 +02:00
Miodrag Milanovic
6e12da3956
machxo2: Initial support for carry chains (CCU2D)
2023-04-06 09:10:14 +02:00
Miodrag Milanovic
f35bdaa527
Update Xilinx cell definitions, fixes #3699
2023-03-23 09:44:36 +01:00
Miodrag Milanovic
ff9f1fb86e
Start unification effort for machxo2 and ecp5
2023-03-20 09:58:41 +01:00
Miodrag Milanovic
4d7e9e2e5d
Add additional iopad_external_pin attributes
2023-03-20 09:17:22 +01:00
Miodrag Milanovic
db367bd69e
Add iopad_external_pin to some basic io primitives
2023-03-20 09:17:22 +01:00
Miodrag Milanovic
10589c57bf
insert IO buffers for ECP5, off by default
2023-03-20 09:17:22 +01:00
Stefan Riesenberger
baa3659ea5
ice40: Fix path delay definitions
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Parallel connections do not allow matching different bit widths.
A full connection has to be used instead.
Allows iverilog to parse the simulation library with hardware path delays enabled.
2023-03-10 10:48:05 +01:00
N. Engelhardt
1a3ff0d926
Merge pull request #3688 from pu-cc/gatemate-reginit
2023-03-01 09:49:14 +01:00
Miodrag Milanović
bb28e48136
Merge pull request #3663 from uis246/master
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gowin: Add new types of oscillator
2023-02-28 06:56:01 +01:00
Miodrag Milanović
4ff9063145
Merge pull request #3652 from martell/elvds
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gowin: Add support for emulated differential output
2023-02-28 06:55:25 +01:00
gatecat
2ab3747cc9
fabulous: Add support for mapping carry chains
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Signed-off-by: gatecat <gatecat@ds0.me>
2023-02-27 09:50:34 +01:00
Oliver Keszöcze
fc56978703
Check DREG attribute
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The DSP48E1 implementation checked the wrong attribute (i.e. CREG) to initialize the D input register. This PR fixes 3680
2023-02-17 17:54:41 +01:00
gatecat
25e7cb3bbb
fabulous: Add CLK to BRAM interface primitives
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Signed-off-by: gatecat <gatecat@ds0.me>
2023-02-16 12:55:53 +01:00
