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mirror of https://github.com/YosysHQ/yosys synced 2025-04-13 12:28:44 +00:00
Code Activity
195 commits 97 branches 53 tags 41 MiB
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3 commits

Author SHA1 Message Date
Clifford Wolf b56e06d2f5 Added support for verilog === operator 2013-05-07 14:35:40 +02:00
Clifford Wolf 7a99349de4 Improvements and bugfixes for generate blocks with local signals 2013-03-26 11:31:34 +01:00
Clifford Wolf 7764d0ba1d initial import 2013-01-05 11:13:26 +01:00