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3 commits

Author SHA1 Message Date
Robert O'Callahan
8b75c06141 Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files. 2025-07-22 10:38:38 +00:00
whitequark
c285880684 fmt: add tests for Verilog round trip of format expressions. 2023-08-11 04:46:52 +02:00
whitequark
67052f62ec fmt: add tests for Yosys evaluation of format expressions. 2023-08-11 04:46:52 +02:00