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Code Activity
5971 commits 122 branches 59 tags 72 MiB
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947 commits

Author SHA1 Message Date
Eddie Hung
dd8d264bf5 install *_nowide.lut files 2019-06-29 19:37:04 -07:00
Eddie Hung
728839d6ca Remove peepopt call in synth_xilinx since already in synth -run coarse 2019-06-28 12:53:38 -07:00
Eddie Hung
03705f69f4 Update synth_ice40 -device doc to be relevant for -abc9 only 2019-06-28 09:49:01 -07:00
Eddie Hung
3f87575cb6 Disable boxing of ECP5 dist RAM due to regression 2019-06-28 09:46:36 -07:00
Eddie Hung
0318860b93 Add write address to abc_scc_break of ECP5 dist RAM 2019-06-28 09:45:48 -07:00
Eddie Hung
b9ddee0c87 Fix DO4 typo 2019-06-28 09:45:40 -07:00
Eddie Hung
00f63d82ce Reduce diff with upstream 2019-06-27 16:13:22 -07:00
Eddie Hung
af8a5ae5fe Extraneous newline 2019-06-27 16:12:20 -07:00
Eddie Hung
4daa746797 Remove noise from ice40/cells_sim.v 2019-06-27 16:11:39 -07:00
Eddie Hung
9398921af1 Refactor for one "abc_carry" attribute on module 2019-06-27 16:07:14 -07:00
Eddie Hung
312c03e4ca Remove redundant doc 2019-06-27 15:28:55 -07:00
Eddie Hung
1237a4c116 Add warning if synth_xilinx -abc9 with family != xc7 2019-06-27 11:22:49 -07:00
Eddie Hung
6c256b8cda Merge origin/master 2019-06-27 11:20:15 -07:00
Eddie Hung
4de25a1949 Add WE to ECP5 dist RAM's abc_scc_break too 2019-06-26 20:02:19 -07:00
Eddie Hung
a7a88109f5 Update comment on boxes 2019-06-26 20:00:15 -07:00
Eddie Hung
b7bef15b16 Add "WE" to dist RAM's abc_scc_break 2019-06-26 19:58:09 -07:00
Eddie Hung
5e1b8d458b Remove unused var 2019-06-26 10:33:07 -07:00
Eddie Hung
988e6163ab Add _nowide variants of LUT libraries in -nowidelut flows 2019-06-26 10:23:29 -07:00
Eddie Hung
741ebba70a Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig 2019-06-26 10:10:16 -07:00
Eddie Hung
799b18263f Merge branch 'koriakin/xc7nocarrymux' into xaig 2019-06-26 10:04:01 -07:00
Eddie Hung
4ce329aefd synth_ecp5 rename -nomux to -nowidelut, but preserve former 2019-06-26 09:33:48 -07:00
Eddie Hung
7389b043c0 Merge branch 'xc7nocarrymux' of https://github.com/koriakin/yosys into koriakin/xc7nocarrymux 2019-06-26 09:33:38 -07:00
David Shah
0dd850e655 abc9: Add wire delays to synth_ice40 
Signed-off-by: David Shah <dave@ds0.me>
 2019-06-26 11:39:44 +01:00
Eddie Hung
480a04cb3c Realistic delays for RAM32X1D too 2019-06-25 09:34:28 -07:00
Eddie Hung
6095357390 Add RAM32X1D box info 2019-06-25 09:34:19 -07:00
Eddie Hung
6f36ec8ecf Merge remote-tracking branch 'origin/master' into xaig 2019-06-25 09:33:11 -07:00
Eddie Hung
2f770b7400 Use LUT delays for dist RAM delays 2019-06-24 23:02:53 -07:00
Eddie Hung
4fadb471a3 Re-enable dist RAM boxes for ECP5 2019-06-24 22:12:50 -07:00
Eddie Hung
a4a7e63d84 Revert "Re-enable dist RAM boxes for ECP5" 
This reverts commit ca0225fcfa.
 2019-06-24 22:10:28 -07:00
Eddie Hung
ca0225fcfa Re-enable dist RAM boxes for ECP5 2019-06-24 21:55:54 -07:00
Eddie Hung
152e682bd5 Add Xilinx dist RAM as comb boxes 2019-06-24 21:54:01 -07:00
Eddie Hung
efd04880db Add RAM32X1D support 2019-06-24 16:16:50 -07:00
Eddie Hung
6027549464 Add comments to ecp5 box 2019-06-22 14:33:47 -07:00
Eddie Hung
792d0670c3 Add comment to xc7 box 2019-06-22 14:28:24 -07:00
Eddie Hung
63182ed57d Fix and cleanup ice40 boxes for carry in/out 2019-06-22 14:27:41 -07:00
Eddie Hung
7903ebe3e0 Carry in/out box ordering now move to end, not swap with end 2019-06-22 14:18:42 -07:00
Eddie Hung
65c022c257 Remove DFF and RAMD box info for now 2019-06-21 20:41:14 -07:00
Eddie Hung
1abe93e48d Merge remote-tracking branch 'origin/master' into xaig 2019-06-21 17:43:29 -07:00
David Shah
a0d3d2bb41 ecp5: Improve mapping of $alu when BI is used 
Signed-off-by: David Shah <dave@ds0.me>
 2019-06-21 09:45:11 +01:00
Eddie Hung
e612dade12 Merge remote-tracking branch 'origin/master' into xaig 2019-06-20 19:00:36 -07:00
Eddie Hung
f11c9a419b Call opt_expr -mux_undef to get rid of 1'bx in muxes prior to abc 2019-06-20 17:38:16 -07:00
acw1251
ce29ede801 Fixed small typo in ice40_unlut help summary 2019-06-19 16:39:46 -04:00
acw1251
0d888ee7ed Fixed the help summary line for a few commands 2019-06-19 15:27:04 -04:00
Eddie Hung
8e0a47fb92 Really permute Xilinx LUT mappings as default LUT6.I5:A6 2019-06-18 11:48:48 -07:00
Eddie Hung
8f5e6d73ff Revert "Fix (do not) permute LUT inputs, but permute mux selects" 
This reverts commit da3d2eedd2.
 2019-06-18 11:35:21 -07:00
Eddie Hung
b304744d15 Clean up 2019-06-18 09:50:37 -07:00
Eddie Hung
da3d2eedd2 Fix (do not) permute LUT inputs, but permute mux selects 2019-06-18 09:49:57 -07:00
Eddie Hung
608a95eb01 Fix copy-pasta issue 2019-06-17 22:29:22 -07:00
Eddie Hung
2a35c4ef94 Permute INIT for +/xilinx/lut_map.v 2019-06-17 22:24:35 -07:00
Eddie Hung
75f8b4cf10 Simplify comment 2019-06-17 19:14:41 -07:00