623 commits

Author	SHA1	Message	Date
Eddie Hung	b47bb5c810	Fix typo in check_label()	2019-10-04 21:43:50 -07:00
Eddie Hung	0acc51c3d8	Add temporary abc9 -nomfs and use for synth_xilinx -abc9	2019-10-04 17:35:43 -07:00
Eddie Hung	9c23811839	Remove DSP48E1 from *_cells_xtra.v	2019-10-04 17:26:42 -07:00
Eddie Hung	5b5756b91e	Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}	2019-09-30 12:52:43 +02:00
Marcin Kościelnicki	4535f2c694	synth_xilinx: Support latches, remove used-up FF init values. ... Fixes #1387.	2019-09-30 12:52:43 +02:00
Eddie Hung	8474c5b366	Merge pull request #1359 from YosysHQ/xc7dsp ... DSP inference for Xilinx (improved for ice40, initial support for ecp5)	2019-09-29 11:26:22 -07:00
Eddie Hung	c372e7baf9	Fix box name	2019-09-27 18:49:45 -07:00
Eddie Hung	b3d8a60cbd	Re-order	2019-09-27 14:32:07 -07:00
Eddie Hung	143f82def2	Missing an '&'	2019-09-26 11:13:08 -07:00
Eddie Hung	033aefc0f4	Typo	2019-09-26 10:34:14 -07:00
Eddie Hung	781dda6175	select once	2019-09-26 10:15:05 -07:00
Eddie Hung	27e5bf5aad	Stop trying to be too smart by prematurely optimising	2019-09-26 09:57:11 -07:00
Eddie Hung	53ea5daa42	Call 'wreduce' after mul2dsp to avoid unextend()	2019-09-25 14:04:36 -07:00
Eddie Hung	93363c94a2	Oops. Actually use __NAME__ in ABC_DSP48E1 macro	2019-09-25 10:33:16 -07:00
Eddie Hung	b41d2fb4e4	Add (* techmap_autopurge *) to abc_unmap.v too	2019-09-23 22:02:22 -07:00
Eddie Hung	11ac37733d	Add techmap_autopurge to outputs in abc_map.v too	2019-09-23 21:56:28 -07:00
Eddie Hung	27167848f4	Revert "Add a xilinx_finalise pass" ... This reverts commit 23d90e0439.	2019-09-23 19:52:55 -07:00
Eddie Hung	0f53893104	Revert "Remove (* techmap_autopurge *) from abc_unmap.v since no effect" ... This reverts commit 67c2db3486.	2019-09-23 19:52:55 -07:00
Eddie Hung	29db96fa1f	Revert "Vivado does not like zero width port connections" ... This reverts commit 895e2befa7.	2019-09-23 19:52:54 -07:00
Eddie Hung	895e2befa7	Vivado does not like zero width port connections	2019-09-23 19:04:07 -07:00
Eddie Hung	67c2db3486	Remove (* techmap_autopurge *) from abc_unmap.v since no effect	2019-09-23 18:56:18 -07:00
Eddie Hung	23d90e0439	Add a xilinx_finalise pass	2019-09-23 18:56:02 -07:00
Eddie Hung	4401e5f142	Grammar	2019-09-20 14:24:31 -07:00
Eddie Hung	289cf688b7	Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40	2019-09-20 09:02:29 -07:00
Eddie Hung	691686f92c	Tidy up, fix undriven	2019-09-19 20:04:52 -07:00
Eddie Hung	1602516a8b	$__ABC_REG to have WIDTH parameter	2019-09-19 19:37:45 -07:00
Eddie Hung	e09f80479e	Fix DSP48E1 timing by breaking P path if MREG or PREG	2019-09-19 18:59:28 -07:00
Eddie Hung	362a803779	Revert "Different approach to timing" ... This reverts commit 41256f48a5.	2019-09-19 18:33:38 -07:00
Eddie Hung	41256f48a5	Different approach to timing	2019-09-19 18:33:29 -07:00
Eddie Hung	5ca25b0c59	Suppress $anyseq warnings	2019-09-19 16:27:14 -07:00
Eddie Hung	595fb611a5	Use (* techmap_autopurge *) to suppress techmap warnings	2019-09-19 15:58:01 -07:00
Eddie Hung	c15a35db84	D is 25 bits not 24 bits wide	2019-09-19 15:55:49 -07:00
Eddie Hung	b88f0f6450	Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dsp	2019-09-19 15:47:41 -07:00
Eddie Hung	95db2489bd	synth_xilinx to infer DSPs for Y_WIDTH >= 9 and [AB]_WIDTH >= 2	2019-09-19 14:58:06 -07:00
Marcin Kościelnicki	13fa873f11	Use extractinv for synth_xilinx -ise	2019-09-19 04:02:48 +02:00
Eddie Hung	fd3b033903	Merge remote-tracking branch 'origin/master' into xc7dsp	2019-09-18 12:23:22 -07:00
Eddie Hung	25e0f0c376	Fix copy-paste	2019-09-18 12:19:16 -07:00
Eddie Hung	b77cf6ba48	Mis-spell	2019-09-18 11:12:46 -07:00
Eddie Hung	e992dbf2c5	Add pattern detection support for DSP48E1 model, check against vendor	2019-09-18 10:45:04 -07:00
Marcin Kościelnicki	09ac36da60	xilinx: Make blackbox library family-dependent. ... Fixes #1246.	2019-09-15 13:37:24 +02:00
Eddie Hung	681be20ca2	Add `undef DSP48E1_INST	2019-09-13 17:07:18 -07:00
Eddie Hung	61877e1370	Fix D -> P{,COUT} delay	2019-09-13 13:32:55 -07:00
Eddie Hung	d0b202c58d	Add no MULT no DPORT config	2019-09-13 12:05:14 -07:00
Eddie Hung	247a63f55d	Add support for MULT and DPORT	2019-09-13 11:45:55 -07:00
Eddie Hung	e235dd0785	Refine diagram	2019-09-13 09:34:40 -07:00
Eddie Hung	734034a872	Add an ASCII drawing	2019-09-12 18:13:46 -07:00
Eddie Hung	c52863f147	Finish explanation	2019-09-12 18:01:49 -07:00
Eddie Hung	aaeaab4ac0	Rename to techmap_guard	2019-09-12 17:45:02 -07:00
Eddie Hung	6bb8e6a726	Initial DSP48E1 box support	2019-09-12 17:11:01 -07:00
Eddie Hung	3a39073302	Set more ports explicitly	2019-09-12 17:10:43 -07:00