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1989 commits

Author SHA1 Message Date
Robert O'Callahan
b3baba4522
Merge cd370bf6d1 into c2291c10a6 2025-09-10 11:49:17 +02:00
Emil J
5278b9cfe1
Merge pull request #5332 from YosysHQ/parse_specify-rebased 
Add state_dependent_path_declaration so that `ifnone` can be parsed (rebased)
 2025-09-09 21:53:04 +02:00
Robert O'Callahan
9764fa5c41 Remove superfluous/wasteful .c_str()s in log_file_warning() filename parameter 2025-09-09 15:41:03 +02:00
Michael Kupfer
75316e8c49 Add state_dependent_path_declaration so that ifnone can be parsed 2025-09-09 13:04:52 +02:00
Jannis Harder
c468ee7add
Merge pull request #5304 from rocallahan/idstring-stringf 
Support `IdString` parameters in `stringf()` and remove `.c_str()` in a lot of places
 2025-09-08 20:29:20 +02:00
Xing Guo
c30fd46ea3 Fix handling of cases that look like sva labels again. 
Commit c8e0ac0 introduces a regression on handling case exprs that look
like sva labels.  After some debugging, we shouldn't push the identifier
ast node to the ast_stack, otherwise, we will get the following
assertion failure:

```
➜  /tmp yosys -p 'read -sv a1.v'

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2025  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.57+1 (git sha1 baa61a146, clang++ 20.1.8 -fPIC -O3)

-- Running command `read -sv a1.v' --

1. Executing Verilog-2005 frontend: a1.v
Parsing SystemVerilog input from `a1.v' to AST representation.
ERROR: Assert `extra->ast_stack.size() == 1' failed in frontends/verilog/verilog_parser.y:709.
➜  /tmp cat a1.v
module test(input wire A);
  localparam TEST = 1;
  always_comb begin
    case (A)
      TEST: assert(1);
    endcase
  end
endmodule
```

We encountered this issue before but with a different error message[^1],

[^1]: https://github.com/YosysHQ/yosys/issues/862
 2025-09-05 11:54:13 +08:00
Robert O'Callahan
c7df6954b9 Remove .c_str() from stringf parameters 2025-09-01 23:34:42 +00:00
Robert O'Callahan
7814aa0c31 Use fast path for 32-bit Const integer constructor in more places 2025-09-01 02:45:57 +00:00
Robert O'Callahan
24a95bd6cf Update frontends to avoid bits() 2025-09-01 02:45:56 +00:00
Ethan Mahintorabi
d10190606c verilog: Lower required bison version to 3.6 
We're currently on version 3.6 of bison at Google, and Yosys
still correctly builds with it. This should better reflect
the actual requirements rather than an overly restrictive
check. If features from 3.8 are required it seems like bumping
would be appropriate.

Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2025-08-21 08:26:33 +01:00
Ethan Mahintorabi
7f0130efce verilog: Fix missing sstream include 
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2025-08-21 08:26:20 +01:00
Emil J
dbb977aa8b
Merge pull request #5288 from YosysHQ/emil/demote-verilog-parser-errors-again 
verilog: demote some parser errors to warnings again
 2025-08-13 12:52:50 +02:00
Emil J. Tywoniak
1603828b30 verilog_parser: fix locations of warnings for restrict keyword 2025-08-13 10:56:48 +02:00
Emil J. Tywoniak
910ff3ff36 verilog: demote some parser errors to warnings again 2025-08-13 10:54:47 +02:00
Emil J. Tywoniak
8582136a45 simplify: fix $initstate segfault 2025-08-12 12:39:36 +02:00
Emil J. Tywoniak
642e041f77 const2ast: fix for consistency with previous diagnostics behavior 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
99ab73424d verilog_location: rename location to Location to avoid conflict with Pass::location 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
5195f81257 ast: fix import node 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
df8422d244 verilog_lexer: refactor 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
740ed3fc1c ast: refactor 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
646c45e6b8 ast: remove null_check as dead code 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
25d2a8ce3a simplify: simplify 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
97bc0088d8 simplify: std::gcd 2025-08-11 13:34:10 +02:00
Krystine Sherwin
d3e33a3be5 simplify.cc: Drop unused debug prints 
At least the ones added by this PR.  There are some unused debug prints that are *changed* by this PR, but I've left them.
 2025-08-11 13:34:10 +02:00
Krystine Sherwin
9b882c32c1 frontends/ast: More usage of auto 
For consistency.
 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
5b62616b63 preproc: formatting 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
9a10f4c02f verilog_lexer, verilog_parser: remove comment 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
ae65b4fc84 verilog_lexer: fix fallthrough warning 2025-08-11 13:34:10 +02:00
Emil J
39c5c256c0 verilog_lexer: remove comment 
Co-authored-by: KrystalDelusion <93062060+KrystalDelusion@users.noreply.github.com>
 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
abb8b8d28b preproc: formatting 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
85b5a7d08b verilog: fix build dependency graph 2025-08-11 13:34:10 +02:00
Gary Wong
4ffd05af6f verilog: add support for SystemVerilog string literals. 
Differences are new escape sequences (including escaped newline
continuations and hex escapes) and triple-quoted literals.
 2025-08-11 13:34:10 +02:00
garytwong
105a3cd32d verilog: fix string literal regular expression (#5187) 
* verilog: fix string literal regular expression.

A backslash was improperly quoted, causing string literal matching
to fail when the final token before a closing quote was an escaped
backslash.

* verilog: add regression test for string literal regex bug.

Test for bug triggered by escaped backslash immediately before
closing quote (introduced in ca7d94af and fixed by 40aa7eaf).
 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
42b5c14e35 read_verilog, ast: use unified locations in errors and simplify dependencies 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
e6e680cd62 readme, verilog_parser: bison 3.8 and ubuntu 22.04 example 2025-08-11 13:34:10 +02:00
Krystine Sherwin
0f7080ebf8 dpicall.cc: Fix sans-plugin function call 2025-08-11 13:34:10 +02:00
Krystine Sherwin
d2573f168d preproc.cc: Use full path for generated file 
Fixes out-of-tree builds.
 2025-08-11 13:34:10 +02:00
Krystine Sherwin
8e89eab9a2 preproc depends on parser 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
27899180a3 fixup! fixup! ast, read_verilog: unify location types, reduce filename copying 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
87352f97b2 fixup! ast, read_verilog: unify location types, reduce filename copying 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
ecec9a760b ast, read_verilog: unify location types, reduce filename copying 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
8bf750ecbb neater errors, lost in the sauce of source 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
b3bf588966 ast, read_verilog: refactoring 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
84f0c5da73 ast: fix new memory safety bugs from rebase 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
4a00169452 ast: ownership for string values 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
c8e0ac0c61 ast, read_verilog: ownership in AST, use C++ styles for parser and lexer 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
f27309136f Revert "verilog: fix string literal regular expression (#5187)" 
This reverts commit 834a7294b7.
 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
36491569d2 Revert "verilog: add support for SystemVerilog string literals." 
This reverts commit 5feb1a1752.
 2025-08-11 13:34:10 +02:00
Emil J. Tywoniak
98b3316f55 Revert "verilog: fix parser "if" memory errors." 
This reverts commit 34a2abeddb.
 2025-08-11 13:34:09 +02:00
KrystalDelusion
7f0e864d44
Merge pull request #5265 from bhagwat-rahul/fix-package-import 
Support package import
 2025-08-08 09:32:54 +12:00