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Author SHA1 Message Date
Rodrigo Alejandro Melo
eaaba6e091 Added tests/memfile to 'make test' with an extra testcase 
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
 2020-02-01 22:44:06 -03:00
Rodrigo Alejandro Melo
43396fae2c Added a test for the Memory Content File inclusion using $readmemb 
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
 2020-02-01 17:41:10 -03:00
Rodrigo Alejandro Melo
b4c30cfc8d Fixed a bug in the new feature of $readmem[hb] when an empty string is provided 
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
 2020-02-01 17:03:56 -03:00
David Shah
65716c9982 xilinx_dsp: Add multonly scratchpad var to bypass 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-01 15:30:43 +00:00
Marcin Kościelnicki
00fba62711 json: remove the 32-bit parameter special case 
Before, the rules for encoding parameters in JSON were as follows:

- if the parameter is not a string:

  - if it is exactly 32 bits long and there are no z or x bits, emit it
    as an int
  - otherwise, emit it as a string made of 0/1/x/z characters

- if the parameter is a string:

  - if it contains only 0/1/x/z characters, append a space at the end
    to distinguish it from a non-string
  - otherwise, emit it directly

However, this caused a problem in the json11 parser used in nextpnr:
yosys emits unsigned ints, and nextpnr parses them as signed, using
the value of INT_MIN for values that overflow the signed int range.
This caused destruction of LUT5 initialization values.  Since both
nextpnr and yosys parser can also accept 32-bit parameters in the
same encoding as other widths, let's just remove that special case.
The old behavior is still left behind a `-compat-int` flag, in case
someone relies on it.
 2020-02-01 16:16:26 +01:00
Eddie Hung
136842b1ef Merge branch 'master' into eddie/submod_po 2020-02-01 02:14:19 -08:00
Rodrigo Alejandro Melo
d74b9604e3 Modified the new search for files of $readmem[hb] to be backward compatible 
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
 2020-01-31 22:10:51 -03:00
Rodrigo Alejandro Melo
7b3fe404ab $readmem[hb] file inclusion is now relative to the Verilog file 
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
 2020-01-31 18:20:22 -03:00
Eddie Hung
a1c840ca5d
Merge pull request #1668 from gsomlo/gls-abc9-external 
abc9: Fix regression breaking support for use of ABCEXTERNAL
 2020-01-31 09:34:13 +00:00
Stefan Biereigel
3c9371589d add inheritance for pywrap generators 2020-01-30 21:26:37 +01:00
Gabriel Somlo
8106c3d31b abc9: restore ability to use ABCEXTERNAL 
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2020-01-30 15:12:43 -05:00
Claire Wolf
2ce7a0d369
Merge pull request #1667 from YosysHQ/clifford/verificnand 
Add Verific support for OPER_REDUCE_NAND
 2020-01-30 19:55:53 +01:00
Claire Wolf
60876ce183
Merge pull request #1503 from YosysHQ/eddie/verific_help 
`verific` pass to print help message when command syntax error
 2020-01-30 18:05:16 +01:00
Claire Wolf
ffadaddab5
Merge pull request #1654 from YosysHQ/eddie/sby_fix69 
verific: unflatten struct ports
 2020-01-30 18:03:35 +01:00
Claire Wolf
23c44afaed Add Verific support for OPER_REDUCE_NAND 
Signed-off-by: Claire Wolf <clifford@clifford.at>
 2020-01-30 18:01:13 +01:00
Xiretza
90404e1969
Improve ABC repository management in Makefile 
`rev-parse --short` output may have a different abbreviated hash length than
ABCREV, so a simple string comparison always fails, even if the correct
commit is checked out. Pass both commits through rev-parse and then
compare the full hashes instead.

Add an `echo-abc-rev` target so that packaging scripts can set ABCPULL=0 and
handle all the git nastiness themselves.
 2020-01-29 19:10:54 +01:00
Xiretza
2a746234fe
Clean up 'install' Makefile target 
- libyosys.so is now only installed to LIBDIR instead of LIBDIR, BINDIR
  and PYTHON_DESTDIR
- replace mkdir/cp for single files with `install`
 2020-01-29 19:10:54 +01:00
Claire Wolf
1679682fa3 Merge branch 'vector_fix' of https://github.com/Kmanfi/yosys 
Also some minor fixes to the original PR.
 2020-01-29 17:01:24 +01:00
Claire Wolf
4d0118d0c1
Merge pull request #1662 from YosysHQ/dave/opt-reduce-move-check 
opt_reduce: Call check() per run rather than per optimised cell
 2020-01-29 15:27:11 +01:00
Claire Wolf
bc325468e7
Merge pull request #1665 from YosysHQ/clifford/edifkeep 
Preserve wires with keep attribute in EDIF back-end
 2020-01-29 15:25:56 +01:00
Claire Wolf
5f53ea2b5b
Merge pull request #1659 from YosysHQ/clifford/experimental 
Add log_experimental() and experimental() API and "yosys -x"
 2020-01-29 15:25:03 +01:00
N. Engelhardt
177a7cb23e
Merge pull request #1510 from pumbor/master 
handle anonymous unions to fix #1080
 2020-01-29 15:21:28 +01:00
Claire Wolf
50d70288d0 Preserve wires with keep attribute in EDIF back-end 
Signed-off-by: Claire Wolf <clifford@clifford.at>
 2020-01-29 14:07:11 +01:00
Miodrag Milanović
71d148bcaa
Merge pull request #1559 from YosysHQ/efinix_test_fix 
Fix for non-deterministic test
 2020-01-29 11:18:06 +01:00
Eddie Hung
d004953772 Add "help -all" and "help -celltypes" sanity test 2020-01-28 18:11:34 -08:00
Eddie Hung
c5971cb16c synth_xilinx: cleanup help 2020-01-28 17:48:43 -08:00
Eddie Hung
0fd64aab25 synth_xilinx: fix help when no active_design; fixes #1664 2020-01-28 17:41:57 -08:00
Marcin Kościelnicki
7e0e42f907 xilinx: Add simulation model for DSP48 (Virtex 4). 2020-01-29 01:40:00 +01:00
Eddie Hung
a855f23f22 Merge remote-tracking branch 'origin/master' into eddie/opt_merge_init 2020-01-28 12:46:18 -08:00
Eddie Hung
7939727d14
Merge pull request #1660 from YosysHQ/eddie/abc9_unpermute_luts 
Unpermute LUT ordering for ice40/ecp5/xilinx
 2020-01-28 11:55:51 -08:00
Eddie Hung
6d27d43727 Add and use SigSpec::reverse() 2020-01-28 10:37:16 -08:00
Eddie Hung
245b8c4ab6 Fix unresolved conflict from #1573 2020-01-28 10:17:47 -08:00
Miodrag Milanovic
94191a93dd Updated test to use assert-max 2020-01-28 18:26:10 +01:00
Claire Wolf
5c2508cef8 Improve logging use of experimental features 
Signed-off-by: Claire Wolf <clifford@clifford.at>
 2020-01-28 17:51:50 +01:00
Claire Wolf
4ddaa70fd6
Merge pull request #1567 from YosysHQ/eddie/sat_init_warning 
sat: suppress 'Warning: ignoring initial value on non-register: ...' when init[i] = 1'bx
 2020-01-28 17:40:28 +01:00
N. Engelhardt
086c133ea5
Merge pull request #1573 from YosysHQ/eddie/xilinx_tristate 
synth_xilinx: error out if tristate without '-iopad'
 2020-01-28 17:24:54 +01:00
David Shah
6fd9cae5ca opt_reduce: Call check() per run rather than per optimised cell 
Signed-off-by: David Shah <dave@ds0.me>
 2020-01-28 09:42:01 +00:00
Pepijn de Vos
409e532433 redirect fuser stderr to /dev/null 2020-01-28 10:02:41 +01:00
Claire Wolf
8f40113826
Merge pull request #1553 from whitequark/manual-dffx 
Document $dffe, $dffsr, $_DFFE_*, $_DFFSR_* cells
 2020-01-28 09:41:08 +01:00
Eddie Hung
21ce1b37fb abc9_ops: -check for negative arrival/required times 2020-01-27 14:22:46 -08:00
Eddie Hung
e18aeda7ed Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwards 
Just like Verilog...
 2020-01-27 14:02:13 -08:00
Eddie Hung
cfb0366a18 Import tests from #1628 2020-01-27 13:56:16 -08:00
Eddie Hung
ce6a690d27 xilinx/ice40/ecp5: undo permuting LUT masks in lut_map 
Now done in read_aiger
 2020-01-27 13:30:27 -08:00
Eddie Hung
48f3f5213e
Merge pull request #1619 from YosysHQ/eddie/abc9_refactor 
Refactor `abc9` pass
 2020-01-27 13:29:15 -08:00
Eddie Hung
e0bdf5d7a9 Fix typo 2020-01-27 12:30:39 -08:00
Eddie Hung
f2576c096c Merge branch 'eddie/abc9_refactor' into eddie/abc9_required 2020-01-27 12:29:28 -08:00
Eddie Hung
9009b76a69 abc9_ops: add comments 2020-01-27 11:18:21 -08:00
Eddie Hung
f443695a38 Merge remote-tracking branch 'origin/master' into eddie/verific_help 2020-01-27 10:34:10 -08:00
Eddie Hung
d730bba6d2 verific: no help() when no YOSYS_ENABLE_VERIFIC 2020-01-27 10:32:18 -08:00
Eddie Hung
7b445121cc verific: also unflatten for 'hierarchy' flow as per @cliffordwolf 2020-01-27 10:15:22 -08:00