1934 commits

Author	SHA1	Message	Date
Clifford Wolf	d6d0e08834	Fixed make rules for ilang parser	2014-07-22 20:39:37 +02:00
Clifford Wolf	4147b55c23	Added "autoidx" statement to ilang file format	2014-07-21 15:15:18 +02:00
Clifford Wolf	361e0d62ff	Replaced depricated NEW_WIRE macro with module->addWire() calls	2014-07-21 12:42:02 +02:00
Clifford Wolf	1d88f1cf9f	Removed deprecated module->new_wire()	2014-07-21 12:35:06 +02:00
Clifford Wolf	9b183539af	Implemented dynamic bit-/part-select for memory writes	2014-07-17 16:49:23 +02:00
Clifford Wolf	5867f6bcdc	Added support for bit/part select to mem2reg rewriter	2014-07-17 13:49:32 +02:00
Clifford Wolf	6d69d4aaa8	Added support for constant bit- or part-select for memory writes	2014-07-17 13:13:21 +02:00
Clifford Wolf	b171a4c1bc	Added "inout" ports support to read_liberty	2014-07-16 18:12:46 +02:00
Clifford Wolf	5057935722	Set blackbox attribute in "read_liberty -lib"	2014-07-16 18:12:16 +02:00
Clifford Wolf	24f58e57f3	Fixed spelling of "direction" in read_liberty messages	2014-07-16 18:02:28 +02:00
Clifford Wolf	543551b80a	changes in verilog frontend for new $mem/$memwr WR_EN interface	2014-07-16 12:49:50 +02:00
Clifford Wolf	0f9ca49dc6	Added passing of various options to vhdl2verilog	2014-07-12 10:02:39 +02:00
Clifford Wolf	55a1b8dbac	Fixed processing of initial values for block-local variables	2014-07-11 13:05:53 +02:00
Clifford Wolf	ee8ad72fd9	fixed parsing of constant with comment between size and value	2014-07-02 06:27:04 +02:00
Clifford Wolf	076182c34e	Fixed handling of mixed real/int ternary expressions	2014-06-25 10:05:36 +02:00
Clifford Wolf	4fc43d1932	More found_real-related fixes to AstNode::detectSignWidthWorker	2014-06-24 15:08:48 +02:00
Clifford Wolf	65b2e9c064	fixed signdness detection for expressions with reals	2014-06-21 21:41:13 +02:00
Clifford Wolf	80e4594695	Added AstNode::MEM2REG_FL_CMPLX_LHS	2014-06-17 21:39:25 +02:00
Clifford Wolf	798ff88855	Improved handling of relational op of real values	2014-06-17 12:47:51 +02:00
Clifford Wolf	6c17d4f242	Improved ternary support for real values	2014-06-16 15:12:24 +02:00
Clifford Wolf	82bbd2f077	Use undef (x/z vs. NaN) rules for real values from IEEE Std 1800-2012	2014-06-16 15:05:37 +02:00
Clifford Wolf	0c4c79c4c6	Fixed parsing of TOK_INTEGER (implies TOK_SIGNED)	2014-06-16 15:02:40 +02:00
Clifford Wolf	5bfe865cec	Added found_real feature to AstNode::detectSignWidth	2014-06-16 15:00:57 +02:00
Clifford Wolf	4d1df128fa	Improved AstNode::realAsConst for large numbers	2014-06-15 09:27:09 +02:00
Clifford Wolf	7f57bc8385	Improved parsing of large integer constants	2014-06-15 08:48:17 +02:00
Clifford Wolf	48dc6ab98d	Improved AstNode::asReal for large integers	2014-06-15 08:38:31 +02:00
Clifford Wolf	149fe83a8d	improved (fixed) conversion of real values to bit vectors	2014-06-14 21:00:51 +02:00
Clifford Wolf	d5765b5e14	Fixed relational operators for const real expressions	2014-06-14 19:33:58 +02:00
Clifford Wolf	f3b4a9dd24	Added support for math functions	2014-06-14 13:36:23 +02:00
Clifford Wolf	9bd7d5c468	Added handling of real-valued parameters/localparams	2014-06-14 12:00:47 +02:00
Clifford Wolf	fc7b6d172a	Implemented more real arithmetic	2014-06-14 11:27:05 +02:00
Clifford Wolf	442a8e2875	Implemented basic real arithmetic	2014-06-14 08:51:22 +02:00
Clifford Wolf	9dd16fa41c	Added real->int convertion in ast genrtlil	2014-06-14 07:44:19 +02:00
Clifford Wolf	7ef0da32cd	Added Verilog lexer and parser support for real values	2014-06-13 11:29:23 +02:00
Clifford Wolf	482d9208aa	Added read_verilog -sv options, added support for bit, logic, ... allways_ff, always_comb, and always_latch	2014-06-12 11:54:20 +02:00
Clifford Wolf	e275e8eef9	Add support for cell arrays	2014-06-07 11:48:50 +02:00
Clifford Wolf	0b1ce63a19	Added support for repeat stmt in const functions	2014-06-07 10:47:53 +02:00
Clifford Wolf	7c8a7b2131	further improved const function support	2014-06-07 00:02:05 +02:00
Clifford Wolf	5281562d0e	made the generate..endgenrate keywords optional	2014-06-06 23:05:01 +02:00
Clifford Wolf	76da2fe172	improved const function support	2014-06-06 22:55:02 +02:00
Clifford Wolf	5c10d2ee36	fix functions with no block (but single statement, loop, etc.)	2014-06-06 21:29:23 +02:00
Clifford Wolf	ab54ce17c8	improved ast simplify of const functions	2014-06-06 17:40:45 +02:00
Clifford Wolf	b5cd7a0179	added while and repeat support to verilog parser	2014-06-06 17:40:04 +02:00
Clifford Wolf	f9c1cd5edb	Improved error message for options after front-end filename arguments	2014-06-04 09:10:50 +02:00
Johann Glaser	63dfbb18cf	new flags -ignore_miss_func and -ignore_miss_dir for read_liberty	2014-05-28 16:50:13 +02:00
Clifford Wolf	7188542155	Fixed clang -Wdeprecated-register warnings	2014-04-20 14:28:23 +02:00
Clifford Wolf	a1be4816d6	Replaced depricated %name-prefix= bison directive	2014-04-20 14:22:11 +02:00
Clifford Wolf	a3b9692a68	Fixed mapping of Verific WIDE_DFFRS operator	2014-03-20 13:40:01 +01:00
Clifford Wolf	470c2455e4	Fixed mapping of Verific FADD primitive with unconnected outputs	2014-03-20 13:26:52 +01:00
Clifford Wolf	cdf1257565	Progress in Verific bindings	2014-03-17 14:43:16 +01:00