34 commits

Author	SHA1	Message	Date
Eddie Hung	7f33a0294b	Cleanup use of hard-coded default parameters in light of #1945	2020-04-22 12:02:30 -07:00
Eddie Hung	53817b8575	Use new port/param overload in pmg	2019-09-20 14:21:22 -07:00
Eddie Hung	0af64df10c	Account for D port being a constant	2019-08-28 15:32:38 -07:00
Eddie Hung	11e3eb1009	More cleanup	2019-08-28 10:19:35 -07:00
Eddie Hung	c4d1bd988b	Do not use default_params dict, hardcode default values, cleanup	2019-08-28 10:06:40 -07:00
Eddie Hung	c3e9627afe	Always generate if no match	2019-08-28 09:54:56 -07:00
Eddie Hung	e95fb24574	Improve xilinx_srl.fixed generate, add .variable generate	2019-08-26 17:49:08 -07:00
Eddie Hung	e574edc3e9	Populate generate for xilinx_srl.fixed pattern	2019-08-26 14:21:17 -07:00
Eddie Hung	a048fc93e8	Do not allow Q of last cell of variable length SRL to be (* keep *)	2019-08-23 18:15:24 -07:00
Eddie Hung	ee9f6e6243	Also add first.Q to chain_bits since variable length	2019-08-23 18:14:06 -07:00
Eddie Hung	70ce3d0670	Do not enforce !EN_POLARITY on $dffe	2019-08-23 18:11:28 -07:00
Eddie Hung	e081303ee8	Cleanup FDRE matching	2019-08-23 17:23:52 -07:00
Eddie Hung	54488cfb82	Oops don't need a finally block	2019-08-23 16:39:37 -07:00
Eddie Hung	83e2d87fb8	Keep track of bits in variable length chain, to check for taps	2019-08-23 16:21:10 -07:00
Eddie Hung	f2d4814284	Don't forget $dff has no EN	2019-08-23 16:14:57 -07:00
Eddie Hung	2217d926a9	Same for variable length	2019-08-23 16:13:16 -07:00
Eddie Hung	b1caf7be5e	Filter on en_port for fixed length	2019-08-23 16:09:46 -07:00
Eddie Hung	513af10d77	Check clock is consistent	2019-08-23 15:18:26 -07:00
Eddie Hung	c2757613b6	Check for non unique nusers/fanouts	2019-08-23 14:32:36 -07:00
Eddie Hung	242b3083ea	Cope with possibility that D could connect to Q on same cell	2019-08-23 13:06:31 -07:00
Eddie Hung	18b64609c2	xilinx_srl to use 'slice' features of pmgen for word level	2019-08-23 12:22:06 -07:00
Eddie Hung	74bd190d3b	Remove output_bits	2019-08-22 11:14:59 -07:00
Eddie Hung	7d02d17b16	Reuse var	2019-08-21 19:18:40 -07:00
Eddie Hung	5c8344363f	Revert "Trim shiftx_width when upper bits are 1'bx" ... This reverts commit 7e7965ca7b.	2019-08-21 19:18:27 -07:00
Eddie Hung	7e7965ca7b	Trim shiftx_width when upper bits are 1'bx	2019-08-21 18:43:17 -07:00
Eddie Hung	15188033da	Add variable length support to xilinx_srl	2019-08-21 17:34:40 -07:00
Eddie Hung	6d76ae4c65	Rename pattern to fixed	2019-08-21 15:46:58 -07:00
Eddie Hung	b0a3b430bf	attribute -> attr	2019-08-21 15:44:07 -07:00
Eddie Hung	61b4d7ae13	Use Cell::has_keep_attribute()	2019-08-21 15:41:46 -07:00
Eddie Hung	6fa9e03e4c	xilinx_srl to support FDRE and FDRE_1	2019-08-21 15:35:29 -07:00
Eddie Hung	1c7d721558	Reject if not minlen from inside pattern matcher	2019-08-21 14:26:24 -07:00
Eddie Hung	cab2bd083e	Get wire via SigBit	2019-08-21 13:47:47 -07:00
Eddie Hung	52fea5b658	Respect \keep on cells or wires	2019-08-21 13:42:03 -07:00
Eddie Hung	0250712486	Initial progress on xilinx_srl	2019-08-21 12:50:49 -07:00