59 commits

Author	SHA1	Message	Date
Clifford Wolf	5998c101a4	Added $sr, $dffsr and $dlatch cell types	2013-10-18 11:56:16 +02:00
Clifford Wolf	73914d1a41	Added -selected option to various backends	2013-09-03 19:10:11 +02:00
Clifford Wolf	39ee561169	More explicit integer output in verilog backend	2013-08-22 20:31:04 +02:00
Clifford Wolf	7bfc7b61a8	Implemented proper handling of stub placeholder modules	2013-03-28 09:20:10 +01:00
Clifford Wolf	87c7717566	Avoid verilog-2k in verilog backend	2013-03-21 09:51:25 +01:00
Clifford Wolf	11789db206	More support code for $sr cells	2013-03-14 11:15:00 +01:00
Clifford Wolf	441e5fbfca	Fixed a gcc compiler warning [-Wparentheses]	2013-03-03 22:45:06 +01:00
Clifford Wolf	7fccad92f7	Added more help messages	2013-03-01 00:36:19 +01:00
Clifford Wolf	7764d0ba1d	initial import	2013-01-05 11:13:26 +01:00