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Code Activity
yosys/backends/verilog
History
Clifford Wolf 5998c101a4 Added $sr, $dffsr and $dlatch cell types
2013-10-18 11:56:16 +02:00
..
Makefile.inc initial import 2013-01-05 11:13:26 +01:00
verilog_backend.cc Added $sr, $dffsr and $dlatch cell types 2013-10-18 11:56:16 +02:00
verilog_backend.h initial import 2013-01-05 11:13:26 +01:00