92 commits

Author	SHA1	Message	Date
Eddie Hung	e79df5e70e	read_aiger to create sane $lut names, and rename when renaming driving wire	2019-02-19 12:27:50 -08:00
Eddie Hung	0b1fc46ae3	Add comment	2019-02-19 10:24:55 -08:00
Eddie Hung	54f719f446	Get rid of boost dep, fix the FIXMEs for Win32?	2019-02-19 10:19:53 -08:00
Eddie Hung	843e7fc8a7	Fix for using POSIX basename	2019-02-19 09:02:37 -08:00
Eddie Hung	8e1dbfac3a	Missing OSX headers?	2019-02-17 20:59:53 -08:00
Eddie Hung	9268a271fb	read_aiger to ignore line after ands for ascii, not binary	2019-02-17 12:07:14 -08:00
Eddie Hung	82459c16c4	In read_xaiger, do not construct ConstEval for every LUT	2019-02-16 22:22:29 -08:00
Eddie Hung	f60cd4ff9b	read_aiger to ignore output = input of same wire; also create new output for different wire	2019-02-16 21:53:03 -08:00
Eddie Hung	1a25ec4baa	read_aiger to disable log_debug	2019-02-16 13:45:51 -08:00
Eddie Hung	8f36013fac	read_xaiger() to use f.read() not readsome()	2019-02-16 08:58:25 -08:00
Eddie Hung	7523c87780	read_aiger() to cope with constant outputs, mixed wideports, do cleaning	2019-02-16 08:44:11 -08:00
Eddie Hung	8d757224ee	read_aiger with more asserts, and call clean	2019-02-15 11:52:05 -08:00
Eddie Hung	c7ef3863f3	Leave FIXME for clean	2019-02-13 17:19:30 -08:00
Eddie Hung	396da54b52	Use module->addLut()	2019-02-13 17:08:32 -08:00
Eddie Hung	13bf036bd6	Use ConstEval to compute LUT masks	2019-02-13 17:00:00 -08:00
Eddie Hung	f0f5d8a5cc	Merge remote-tracking branch 'origin/read_aiger' into xaig	2019-02-13 14:09:36 -08:00
Eddie Hung	e9df9a466a	Add support for read_aiger -wideports	2019-02-12 12:58:10 -08:00
Eddie Hung	06ba81d41f	Add support for read_aiger -map	2019-02-12 12:16:37 -08:00
Eddie Hung	77d3627753	Parse 'm' in xaiger	2019-02-12 09:36:22 -08:00
Eddie Hung	6faad18874	Merge branch 'read_aiger' of github.com:eddiehung/yosys into read_aiger	2019-02-12 09:21:46 -08:00
Eddie Hung	a2ae393811	Use module->add{Not,And}Gate() functions	2019-02-12 09:21:15 -08:00
Eddie Hung	0124512f28	Add read_xaiger	2019-02-11 15:19:17 -08:00
Eddie Hung	04c580fde7	Do not break for constraints	2019-02-11 13:28:00 -08:00
Eddie Hung	727ba52504	No increment line_count for binary ANDs	2019-02-11 13:24:21 -08:00
Eddie Hung	bb4164481d	Do not ignore newline after AND in binary AIG	2019-02-11 11:51:44 -08:00
Eddie Hung	8886fa5506	addDff -> addDffGate as per @daveshah1	2019-02-08 13:17:53 -08:00
Eddie Hung	afc3c4b613	Fix tabulation	2019-02-08 13:17:02 -08:00
Eddie Hung	aa66d8f12f	-module_name arg to go before -clk_name	2019-02-08 12:49:55 -08:00
Eddie Hung	fb8ad440a3	Allow module name to be determined by argument too	2019-02-08 12:40:43 -08:00
Eddie Hung	f1befe1b44	Refactor into AigerReader class	2019-02-08 12:04:26 -08:00
Eddie Hung	2a8cc36578	Parse binary AIG files	2019-02-08 11:45:16 -08:00
Eddie Hung	09d758f0a3	Refactor to parse_aiger_header()	2019-02-08 10:54:31 -08:00
Eddie Hung	36c56bf412	Add comment	2019-02-08 08:37:44 -08:00
Eddie Hung	5e24251a61	Handle reset logic in latches	2019-02-08 08:37:18 -08:00
Eddie Hung	652e414392	Change literal vars from int to unsigned	2019-02-08 08:09:30 -08:00
Eddie Hung	fafa972238	Create clk outside of latch loop	2019-02-08 08:08:49 -08:00
Eddie Hung	02f603ac1a	Handle latch symbols too	2019-02-08 08:05:27 -08:00
Eddie Hung	5a593ff41c	Remove return after log_error	2019-02-08 08:04:48 -08:00
Eddie Hung	6dbeda1807	Add support for symbol tables	2019-02-08 08:03:40 -08:00
Eddie Hung	791f93181d	Stub for binary AIGER	2019-02-08 07:31:04 -08:00
Eddie Hung	40db2f2eb6	Refactor	2019-02-06 14:58:47 -08:00
Eddie Hung	cc0b723484	WIP	2019-02-06 12:19:48 -08:00