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Author SHA1 Message Date
Eddie Hung
ab667d3d47 Call abc9 with "&write -n", and parse_xaiger() to cope 2019-12-06 16:35:57 -08:00
Eddie Hung
c767525441 Remove creation of $abc9_control_wire 2019-12-06 16:23:09 -08:00
Eddie Hung
69d8c1386a Do not connect undriven POs to 1'bx 2019-12-06 16:21:06 -08:00
Eddie Hung
fce527f4f7 Fix abc9 re-integration, remove abc9_control_wire, use cell->type as 
as part of clock domain for mergeability class
 2019-12-06 16:20:18 -08:00
Eddie Hung
1f96de04c9 Fix writing non-whole modules, including inouts and keeps 2019-12-06 16:19:10 -08:00
Jan Kowalewski
dcb30b5f4a tests: arch: xilinx: Change order of arguments in macc.sh 2019-12-06 09:15:49 +01:00
Eddie Hung
ec0acc9f85 abc9 to use mergeability class to differentiate sync/async 2019-12-06 00:12:37 -08:00
Eddie Hung
a682a3cf93 write_xaiger to support part-selected modules again 2019-12-05 17:54:43 -08:00
Eddie Hung
01a3cc29ba abc9 to do clock partitioning again 2019-12-05 17:26:22 -08:00
Eddie Hung
02786b0aa0 Remove clkpart 2019-12-05 17:25:26 -08:00
Eddie Hung
864bff14f1 Revert "Special abc9_clock wire to contain only clock signal" 
This reverts commit 6a2eb5d8f9.
 2019-12-05 11:11:53 -08:00
Clifford Wolf
7dece7955e
Merge pull request #1551 from whitequark/manual-cell-operands 
Clarify semantics of comb cells, in particular shifts
 2019-12-05 08:24:24 -08:00
Eddie Hung
a7e0cca480 Merge SB_CARRY+SB_LUT4's attributes when creating $__ICE40_CARRY_WRAPPER 2019-12-05 07:01:18 -08:00
Eddie Hung
d8fbf88980 Add WIP test for unwrapping $__ICE40_CARRY_WRAPPER 2019-12-05 07:01:02 -08:00
whitequark
72a5674c03 manual: document $dffe, $dffsr, $_DFFE_*, $_DFFSR_* cells. 2019-12-05 10:28:43 +00:00
Eddie Hung
0d248dd7ba Missing wire declaration 2019-12-04 23:04:40 -08:00
Eddie Hung
19bc429482 abc9_map.v to transform INIT=1 to INIT=0 2019-12-04 21:36:41 -08:00
Eddie Hung
258a34e6f1 Oh deary me 2019-12-04 20:33:24 -08:00
Eddie Hung
c8a7bc5d3a Bump ABC to get "&verify -s" fix 2019-12-04 16:37:56 -08:00
Eddie Hung
b43986c5a1 output reg Q -> output Q to suppress warning 2019-12-04 16:34:34 -08:00
Eddie Hung
31ef4cc704 abc9_map.v to do `zinit' and make INIT = 1'b0 2019-12-04 16:11:02 -08:00
whitequark
e97e33d00d kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr. 
Before this commit, these cells would accept any \B_SIGNED and in
case of \B_SIGNED=1, would still treat the \B input as unsigned.

Also fix the Verilog frontend to never emit such constructs.
 2019-12-04 11:59:36 +00:00
whitequark
ec4c9267b3 manual: document behavior of many comb cells more precisely. 2019-12-04 11:32:14 +00:00
Marcin Kościelnicki
fcce94010f
xilinx: Add tristate buffer mapping. (#1528) 
Fixes #1225.
 2019-12-04 09:44:00 +01:00
Marcin Kościelnicki
2abe38e73e
iopadmap: Refactor and fix tristate buffer mapping. (#1527) 
The previous code for rerouting wires when inserting tristate buffers
was overcomplicated and didn't handle all cases correctly (in
particular, only cell connections were rewired — internal connections
were not).
 2019-12-04 08:44:08 +01:00
Marcin Kościelnicki
10014e2643
xilinx: Add models for LUTRAM cells. (#1537) 2019-12-04 06:31:09 +01:00
Eddie Hung
c6ee2fb482 Cleanup 2019-12-03 19:21:47 -08:00
Eddie Hung
d66d06b91d Add assertion 2019-12-03 19:21:42 -08:00
Eddie Hung
df52bc80d8 write_xaiger to consume abc9_init attribute for abc9_flops 2019-12-03 18:47:44 -08:00
Eddie Hung
a181ff66d3 Add abc9_init wire, attach to abc9_flop cell 2019-12-03 18:47:09 -08:00
Eddie Hung
f98aa1c13f Revert "Add INIT value to abc9_control" 
This reverts commit 19bfb41958.
 2019-12-03 15:40:44 -08:00
Eddie Hung
5165049410 Update ABCREV for upstream bugfix 2019-12-03 15:09:33 -08:00
Eddie Hung
67f1ce2d43 Check SB_CARRY name also preserved 2019-12-03 14:51:39 -08:00
Eddie Hung
ed3f359175 $__ICE40_CARRY_WRAPPER to use _TECHMAP_REPLACE_ for SB_CARRY to preserve 
name and attr
 2019-12-03 14:49:10 -08:00
Eddie Hung
1ea9ce0ad7 ice40_opt to ignore (* keep *) -ed cells 2019-12-03 14:48:39 -08:00
Eddie Hung
5897b918b3 ice40_wrapcarry to preserve SB_CARRY's attributes 2019-12-03 14:48:11 -08:00
Eddie Hung
8de17877d4 Add testcase 2019-12-03 14:48:00 -08:00
Eddie Hung
0add5965c7 techmap abc_unmap.v before xilinx_srl -fixed 2019-12-03 14:27:45 -08:00
Clifford Wolf
2ec6d832dc
Merge pull request #1524 from pepijndevos/gowindffinit 
Gowin: add and test DFF init values
 2019-12-03 08:43:18 -08:00
Pepijn de Vos
a7d34a7cb5 update test 2019-12-03 16:56:15 +01:00
Pepijn de Vos
a3b25b4af8 Use -match-init to not synth contradicting init values 2019-12-03 15:12:25 +01:00
Eddie Hung
19bfb41958 Add INIT value to abc9_control 2019-12-02 14:17:06 -08:00
David Shah
7f35b2ff62
Merge pull request #1542 from YosysHQ/dave/abc9-loop-fix 
abc9: Fix breaking of SCCs
 2019-12-02 10:20:21 +00:00
Eddie Hung
a265a84632 Use pool instead of std::set for determinism 2019-12-02 01:28:28 -08:00
Eddie Hung
6398b7c17c Cleanup 2019-12-01 23:43:28 -08:00
Eddie Hung
1d87488795 Use pool instead of std::set for determinism 2019-12-01 23:26:17 -08:00
Eddie Hung
4ac1b92df3 Use pool<> not std::set<> for determinism 2019-12-01 23:19:32 -08:00
Clifford Wolf
cacf870d85
Merge pull request #1539 from YosysHQ/mwk/ilang-bounds-check 
read_ilang: do bounds checking on bit indices
 2019-12-01 16:30:48 -08:00
David Shah
e9ce4e658b abc9: Fix breaking of SCCs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-12-01 20:44:56 +00:00
Miodrag Milanović
5f4c35c753
Merge pull request #1540 from YosysHQ/mwk/xilinx-bufpll 
xilinx: Add missing blackbox cell for BUFPLL.
 2019-11-29 17:33:41 +01:00