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Author	SHA1	Message	Date
Clifford Wolf	a7c6b37abf	Added "kernel/yosys.h" and "kernel/yosys.cc"	2014-07-30 14:10:15 +02:00
Clifford Wolf	273383692a	Added "test_cell" command	2014-07-29 22:07:41 +02:00
Clifford Wolf	e6df25bf74	Renamed "write_autotest" to "test_autotb" and moved to passes/tests/	2014-07-29 21:12:50 +02:00
Clifford Wolf	e605af8a49	Fixed Verilog pre-processor for files with no trailing newline	2014-07-29 20:14:25 +02:00
Clifford Wolf	2145e57ef0	Bugfix in simlib.v for iverilog	2014-07-29 19:23:31 +02:00
Clifford Wolf	77e2d39cd0	Allow "hierarchy -generate" for $__ cells	2014-07-29 16:35:13 +02:00
Clifford Wolf	03c96f9ce7	Added "techmap -map %{design-name}"	2014-07-29 16:35:13 +02:00
Clifford Wolf	397b00252d	Added $shift and $shiftx cell types (needed for correct part select behavior)	2014-07-29 16:35:13 +02:00
Clifford Wolf	48822e79a3	Removed left over debug code	2014-07-28 19:38:30 +02:00
Clifford Wolf	ec58965967	Fixed part selects of parameters	2014-07-28 19:24:28 +02:00
Clifford Wolf	a03297a7df	Set results of out-of-bounds static bit/part select to undef	2014-07-28 16:09:50 +02:00
Clifford Wolf	55521c085a	Fixed RTLIL code generator for part select of parameter	2014-07-28 15:31:19 +02:00
Clifford Wolf	0598bc8708	Fixed width detection for part selects	2014-07-28 15:19:34 +02:00
Clifford Wolf	27a872d1e7	Added support for "upto" wires to Verilog front- and back-end	2014-07-28 14:25:03 +02:00
Clifford Wolf	3c45277ee0	Added wire->upto flag for signals such as "wire [0:7] x;"	2014-07-28 12:12:13 +02:00
Clifford Wolf	7bd2d1064f	Using log_assert() instead of assert()	2014-07-28 11:27:48 +02:00
Clifford Wolf	d86a25f145	Added std::initializer_list<> constructor to SigSpec	2014-07-28 10:52:58 +02:00
Clifford Wolf	f99495a895	Added cover() to all SigSpec constructors	2014-07-28 10:52:30 +02:00
Clifford Wolf	ee65dea738	Fixed signdness detection of expressions with bit- and part-selects	2014-07-28 10:10:08 +02:00
Clifford Wolf	c469be883b	Improvements in tests/vloghtb	2014-07-28 09:15:40 +02:00
Clifford Wolf	8b0f50792c	Added techmap -extern	2014-07-27 21:31:18 +02:00
Clifford Wolf	c4bdba78cb	Added proper Design->addModule interface	2014-07-27 21:12:09 +02:00
Clifford Wolf	5da343b7de	Added topological sorting to techmap	2014-07-27 16:43:39 +02:00
Clifford Wolf	0c86d6106c	Added SigPool::check(bit)	2014-07-27 15:38:02 +02:00
Clifford Wolf	ddd31a0b66	Small improvements in PerformanceTimer API	2014-07-27 15:14:02 +02:00
Clifford Wolf	77a1462f2d	Fixed bug in opt_clean	2014-07-27 15:13:29 +02:00
Clifford Wolf	d07a871d35	Improved performance of opt_const on large modules	2014-07-27 14:50:25 +02:00
Clifford Wolf	4be645860b	Added RTLIL::SigSpec::remove_const() handling of packed SigSpecs	2014-07-27 14:47:48 +02:00
Clifford Wolf	cbc3a46a97	Added RTLIL::SigSpecConstIterator	2014-07-27 14:47:23 +02:00
Clifford Wolf	dbb3556e3f	Fixed a bug in opt_clean and some RTLIL API usage cleanups	2014-07-27 13:19:05 +02:00
Clifford Wolf	d878fcbdc7	Added log_cmd_error_expection	2014-07-27 12:05:50 +02:00
Clifford Wolf	7661ded8dd	Fixed verific bindings for new RTLIL api	2014-07-27 12:00:28 +02:00
Clifford Wolf	6b34215efd	Fixed ilang parser for new RTLIL API	2014-07-27 11:56:35 +02:00
Clifford Wolf	49f72421d5	Using new obj iterator API in a few places	2014-07-27 11:32:42 +02:00
Clifford Wolf	675cb93da9	Added RTLIL::Module::wire(id) and cell(id) lookup functions	2014-07-27 11:18:31 +02:00
Clifford Wolf	0bd8fafbd2	Added RTLIL::Design::modules()	2014-07-27 11:18:30 +02:00
Clifford Wolf	10e5791c5e	Refactoring: Renamed RTLIL::Design::modules to modules_	2014-07-27 11:18:30 +02:00
Clifford Wolf	d088854b47	Added conversion from ObjRange to std::vector and std::set	2014-07-27 11:18:30 +02:00
Clifford Wolf	1c8fdaeef8	Added RTLIL::ObjIterator and RTLIL::ObjRange	2014-07-27 11:18:30 +02:00
Clifford Wolf	ddc5b41848	Using std::move() in SigSpec move constructor	2014-07-27 09:20:59 +02:00
Clifford Wolf	7f3dc86ecd	Added RTLIL::SigSpec move constructor and move assignment operator	2014-07-27 02:11:57 +02:00
Clifford Wolf	c91570bde3	Mostly cosmetic changes to rtlil.h	2014-07-27 02:00:04 +02:00
Clifford Wolf	4c4b602156	Refactoring: Renamed RTLIL::Module::cells to cells_	2014-07-27 01:51:45 +02:00
Clifford Wolf	f9946232ad	Refactoring: Renamed RTLIL::Module::wires to wires_	2014-07-27 01:49:51 +02:00
Clifford Wolf	d7916a49af	New message for completion of build	2014-07-26 21:35:16 +02:00
Clifford Wolf	d68c993ed2	Changed more code to the new RTLIL::Wire constructors	2014-07-26 21:30:38 +02:00
Clifford Wolf	946ddff9ce	Changed a lot of code to the new RTLIL::Wire constructors	2014-07-26 20:12:50 +02:00
Clifford Wolf	d49dec1f86	Added tests/various/.gitignore	2014-07-26 17:43:41 +02:00
Clifford Wolf	b21ebe1859	Added tests/various/submod_extract.ys	2014-07-26 17:22:18 +02:00
Clifford Wolf	267c615640	Added support for here documents	2014-07-26 17:21:40 +02:00