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Author	SHA1	Message	Date
Diego	f9272fc56d	GoWin enablement: DRAM, initial BRAM, DRAM init, DRAM sim and synth_gowin flow	2019-04-12 23:40:02 -05:00
Eddie Hung	fecafb2207	Forgot backslashes	2019-04-12 18:22:44 -07:00
Eddie Hung	9bfcd80063	Handle __dummy_o__ and __const[01]__ in read_aiger not abc	2019-04-12 18:21:16 -07:00
Eddie Hung	482a60825b	abc to ignore __dummy_o__ and __const[01]__ when re-integrating	2019-04-12 18:16:50 -07:00
Eddie Hung	fe0b421212	Output __const0__ and __const1__ CIs	2019-04-12 18:16:25 -07:00
Eddie Hung	c776db3320	Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig	2019-04-12 17:09:24 -07:00
Eddie Hung	acf3f5694b	Fix inout handling for -map option	2019-04-12 17:02:24 -07:00
Eddie Hung	a16123cc7d	Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig	2019-04-12 16:31:12 -07:00
Eddie Hung	d880f73c79	Merge remote-tracking branch 'origin/master' into xaig	2019-04-12 16:30:53 -07:00
Eddie Hung	88d43a519b	Use -map instead of -symbols for aiger	2019-04-12 16:29:14 -07:00
Eddie Hung	686e772f0b	ci_bits and co_bits now a list, order is important for ABC	2019-04-12 16:17:48 -07:00
Eddie Hung	ada130b459	Also cope with duplicated CIs	2019-04-12 16:17:12 -07:00
Eddie Hung	c748391730	WIP	2019-04-12 14:13:11 -07:00
Eddie Hung	941365b4bb	Comment out	2019-04-12 12:29:04 -07:00
Eddie Hung	04e466d5e4	Add support for synth_xilinx -abc9 and ignore abc9 -dress opt	2019-04-12 12:28:37 -07:00
Eddie Hung	1c6f0cffd9	Cope with an output having same name as an input (i.e. CO)	2019-04-12 12:27:07 -07:00
Eddie Hung	f77da46a87	Merge remote-tracking branch 'origin/master' into xaig	2019-04-12 12:21:48 -07:00
Eddie Hung	db1a5ec6a2	Merge pull request #928 from litghost/add_xc7_sim_models ... Add additional cells sim models for core 7-series primitives.	2019-04-12 11:52:45 -07:00
Eddie Hung	ca8ef92a82	PI before CI	2019-04-12 10:36:05 -07:00
Eddie Hung	8228b593ef	Merge remote-tracking branch 'origin/master' into xc7mux	2019-04-12 09:46:07 -07:00
Keith Rothman	1f9235ede5	Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra. ... Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>	2019-04-12 09:35:15 -07:00
Clifford Wolf	9d6586b4e1	Merge pull request #933 from dh73/master ... Fixing issues in CycloneV cell sim	2019-04-12 14:57:36 +02:00
Clifford Wolf	48bc203653	Merge pull request #932 from YosysHQ/eddie/fixdlatch ... Recognise default entry in case even if all cases covered (fix for #931)	2019-04-12 14:57:01 +02:00
Diego	643ae9bfc5	Fixing issues in CycloneV cell sim	2019-04-11 19:59:03 -05:00
Eddie Hung	3c1f1a6605	Fix ordering of when to insert zero index	2019-04-11 16:25:59 -07:00
Eddie Hung	53513c52df	Merge remote-tracking branch 'origin/pmux2shiftx' into xc7mux	2019-04-11 16:21:01 -07:00
Eddie Hung	f587950bde	More unused	2019-04-11 16:20:43 -07:00
Eddie Hung	35181a7866	Merge remote-tracking branch 'origin/pmux2shiftx' into xc7mux	2019-04-11 16:18:45 -07:00
Eddie Hung	b15b410b41	Remove unused	2019-04-11 16:18:01 -07:00
Eddie Hung	b1f1db2fcf	Fixes	2019-04-11 16:17:09 -07:00
Eddie Hung	e8c26f2839	WIP	2019-04-11 15:52:04 -07:00
Eddie Hung	09e7eb7aed	Spelling fixes	2019-04-11 15:09:13 -07:00
Eddie Hung	7685469ee2	Add default entry to testcase	2019-04-11 15:03:40 -07:00
Eddie Hung	adc6efb584	Recognise default entry in case even if all cases covered (#931)	2019-04-11 12:34:51 -07:00
Eddie Hung	233edf00fe	Fix cells_map.v some more	2019-04-11 10:48:14 -07:00
Eddie Hung	8658b56a08	More fine tuning	2019-04-11 10:08:05 -07:00
Eddie Hung	0ec8564099	Fix cells_map.v	2019-04-11 10:04:58 -07:00
Eddie Hung	bca3779657	Fix typo	2019-04-11 09:25:19 -07:00
Eddie Hung	87b8d29a90	Juggle opt calls in synth_xilinx	2019-04-11 09:13:39 -07:00
Eddie Hung	227cc54c16	Merge branch 'xaig' into xc7mux	2019-04-10 18:07:11 -07:00
Eddie Hung	2217d59e29	Add non-input bits driven by unrecognised cells as ci_bits	2019-04-10 18:06:33 -07:00
Eddie Hung	cd7b2de27f	WIP for cells_map.v -- maybe working?	2019-04-10 18:05:09 -07:00
Eddie Hung	3d577586fd	Try splitting $shiftx with Y_WIDTH > 1 into Y_WIDTH = 1	2019-04-10 16:15:23 -07:00
Eddie Hung	3f5dab0d09	Fix for when B_SIGNED = 1	2019-04-10 14:51:10 -07:00
Eddie Hung	32561332b2	Update doc for synth_xilinx	2019-04-10 14:48:58 -07:00
Eddie Hung	bf92218e0f	Merge branch 'xaig' into xc7mux	2019-04-10 14:03:09 -07:00
Eddie Hung	1a49cf29d8	parse_aiger() to rename all $lut cells after "clean"	2019-04-10 14:02:23 -07:00
Eddie Hung	17a02df05c	ff_map.v after abc	2019-04-10 12:36:06 -07:00
Eddie Hung	1ec949d5ed	Tidy up	2019-04-10 09:02:42 -07:00
Eddie Hung	526aef9c2a	Move map_cells to before map_luts	2019-04-10 08:50:31 -07:00