Catherine
a5441bc00c
fmt: FmtPart::{STRING→LITERAL},{CHARACTER→STRING}.
...
Before this commit, the `STRING` variant inserted a literal string;
the `CHARACTER` variant inserted a string. This commit renames them
to `LITERAL` and `STRING` respectively.
2024-04-02 12:13:22 +02:00
N. Engelhardt
c98cdc2a42
Merge pull request #4184 from povik/check-loop-edges
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Use cell edges data in `check`, improve messages
2024-03-25 16:19:35 +01:00
Krystine Sherwin
d2bf5a83af
Merge branch 'origin/master' into krys/docs
2024-03-18 10:39:30 +13:00
Miodrag Milanovic
5e05300e7b
fix compile warning
2024-03-11 10:55:09 +01:00
Martin Povišer
d01728aaa5
celledges: Register async FF paths
2024-03-11 10:45:36 +01:00
Martin Povišer
87e72ef86f
celledges: Add read ports arst paths
2024-03-11 10:45:17 +01:00
Martin Povišer
4a10e78777
celledges: Emit empty edges for write/init ports
2024-03-11 10:45:17 +01:00
Martin Povišer
3a1ef44564
celledges: Describe asynchronous read ports
2024-03-11 10:45:17 +01:00
Martin Povišer
6e5f40e364
utils: Save detected loops with their nodes in-order
2024-03-11 10:43:49 +01:00
N. Engelhardt
d70113a909
Merge pull request #3972 from nakengelhardt/celledges_shift_ops
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celledges: support shift ops
2024-03-08 09:35:47 +01:00
Krystine Sherwin
1455941ab9
Merge branch 'master' into krys/docs
2024-03-05 05:48:46 +13:00
Jason Thorpe
a02d4e7853
Tweak the FreeBSD version of proc_self_dirname() to work on NetBSD use it.
2024-03-03 07:54:39 -08:00
Martin Povišer
dd11a5a37c
Shrink further
2024-02-26 16:25:46 +01:00
Martin Povišer
b5b737de38
Shrink a bit more
2024-02-22 22:20:35 +01:00
Martin Povišer
f7737a12ca
Cut down startup banner
2024-02-22 22:14:32 +01:00
Martin Povišer
173f4b5fbd
Bump Claire's notices
2024-02-22 22:03:44 +01:00
Martin Povišer
f5013d035e
rtlil: Fix Const hashing omission
2024-02-19 15:45:54 +01:00
Jannis Harder
3473b6dd27
Merge pull request #4206 from povik/cli-crashes
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driver: Fix crashes on missing cli arguments
2024-02-12 16:39:38 +01:00
Martin Povišer
54a97f8bb7
driver: Fix crashes on missing cli arguments
2024-02-12 14:56:23 +01:00
Miodrag Milanović
edb95c69a9
Merge pull request #4084 from jix/scopeinfo
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$scopeinfo support
2024-02-12 09:51:22 +01:00
Martin Povišer
66479a2232
hashlib: Add missing stdint.h include
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We use `uint32_t` `uint64_t` etc. so add an explicit include.
2024-02-08 14:27:12 +00:00
Miodrag Milanovic
a38273c19d
add log_suppressed and fixed formatting
2024-02-08 12:19:42 +01:00
Miodrag Milanovic
2797d67569
Move block and change message to debug
2024-02-08 09:19:19 +01:00
Miodrag Milanovic
f785eef685
Merge branch 'master' of github.com:hakan-demirli/yosys into xdg
2024-02-08 09:03:52 +01:00
Jannis Harder
0d5b48de98
Add scopeinfo index/lookup utils
2024-02-06 18:01:26 +01:00
Jannis Harder
f728927307
Add builtin celltype $scopeinfo
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Only declares the cell interface, doesn't make anything use or
understand $scopeinfo yet.
2024-02-06 17:51:24 +01:00
Claire Xen
1b73b5beb7
Merge pull request #4174 from YosysHQ/claire/overwrite
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Add API to overwrite existing pass from plugin
2024-02-05 23:49:24 +01:00
hakan-demirli
7dbe288d6f
fix: descriptive logs
2024-02-02 02:39:04 +03:00
hakan-demirli
c1d3288654
chore: use similar variable/function names
2024-02-02 01:25:58 +03:00
Catherine
c7bf0e3b8f
Add new $check cell to represent assertions with a message.
2024-02-01 20:10:39 +01:00
hakan-demirli
dd5dc06863
fix: save history file on windows
2024-01-31 20:14:32 +03:00
hakan-demirli
820232eaca
fix: function naming and locations
2024-01-31 19:50:31 +03:00
hakan-demirli
8c731658c2
Merge branch 'YosysHQ:master' into master
2024-01-31 01:03:59 +03:00
hakan-demirli
039634d973
feat: mkdir with tree
2024-01-31 01:03:01 +03:00
Claire Xenia Wolf
4fa314c0bd
Add API to overwrite existing pass from plugin
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2024-01-30 17:51:11 +01:00
N. Engelhardt
027cb31e9d
Merge pull request #4161 from YosysHQ/nak/add_sig_extract_asserts
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SigSpec/SigChunk::extract(): assert offset/length are not out of range
2024-01-29 16:11:01 +01:00
Martin Povišer
c035289383
rtlil: Do not create dummy wires when deleting wires in connections
2024-01-29 11:25:54 +01:00
Martin Povišer
d6600fb1d5
rtlil: Fix handling of connections on wire deletion
2024-01-29 11:25:54 +01:00
N. Engelhardt
efe4d6dbdc
SigSpec/SigChunk::extract(): assert offset/length are not out of range
2024-01-25 12:28:17 +01:00
Krystine Sherwin
65bb0d3059
Docs: updating to current 'master'
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Pulling for #4133 and removing related TODO.
2024-01-22 11:18:07 +13:00
Catherine
b74d33d1b8
fmt: rename TIME to VLOG_TIME.
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The behavior of these format specifiers is highly specific to Verilog
(`$time` and `$realtime` are only defined relative to `$timescale`)
and may not fit other languages well, if at all. If they choose to use
it, it is now clear what they are opting into.
This commit also simplifies the CXXRTL code generation for these format
specifiers.
2024-01-19 15:12:05 +00:00
Martin Povišer
134eb15c7e
celledges: Clean up shift rules
2024-01-19 11:08:31 +01:00
Catherine
a33acb7cd9
cxxrtl: refactor the formatter and use a closure.
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This commit achieves three roughly equally important goals:
1. To bring the rendering code in kernel/fmt.cc and in cxxrtl.h as close
together as possible, with an ideal of only having the bigint library
as the difference between the render functions.
2. To make the treatment of `$time` and `$realtime` in CXXRTL closer to
the Verilog semantics, at least in the formatting code.
3. To change the code generator so that all of the `$print`-to-`string`
conversion code is contained inside of a closure.
There are two reasons to aim for goal (3):
a. Because output redirection through definition of a global ostream
object is neither convenient nor useful for environments where
the output is consumed by other code rather than being printed on
a terminal.
b. Because it may be desirable to, in some cases, ignore the `$print`
cells that are present in the netlist based on a runtime decision.
This is doubly true for an upcoming `$check` cell implementing
assertions, since failing a `$check` would by default cause a crash.
2024-01-16 16:35:51 +00:00
hakan-demirli
e093f57c10
fix: fail if neither HOME nor XDG_STATE_HOME are set
2024-01-08 08:49:04 +03:00
hakan-demirli
54c3b63d24
fix: third time is the charm
2024-01-07 14:34:27 +03:00
hakan-demirli
31b45c9555
fix: xdg spec for hist
2024-01-07 14:17:48 +03:00
hakan-demirli
bcf1c7b879
Merge branch 'YosysHQ:master' into master
2024-01-07 14:08:35 +03:00
Martin Povišer
a96c257b3f
celledges: Add messy rules that do pass the tests
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This passes `test_cell -edges` on all the types of shift cells.
2024-01-04 19:34:15 +01:00
Claire Xenia Wolf
fb72dc1a40
Add constexpr hashlib default constructors
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2023-12-29 19:20:44 +01:00
hakan-demirli
f50e8a3c1b
Follow the XDG Base Directory Specification
2023-12-21 21:44:02 +03:00
