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fmt: rename TIME to VLOG_TIME.

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The behavior of these format specifiers is highly specific to Verilog
(`$time` and `$realtime` are only defined relative to `$timescale`)
and may not fit other languages well, if at all. If they choose to use
it, it is now clear what they are opting into.

This commit also simplifies the CXXRTL code generation for these format
specifiers.
This commit is contained in:
Catherine 2024-01-19 13:33:14 +00:00
parent 08d7f54726
commit b74d33d1b8
5 changed files with 37 additions and 33 deletions
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26
kernel/fmt.cc
View file

@ -110,9 +110,9 @@ void Fmt::parse_rtlil(const RTLIL::Cell *cell) {
} else if (fmt[i] == 'c') {
part.type = FmtPart::CHARACTER;
} else if (fmt[i] == 't') {
part.type = FmtPart::TIME;
part.type = FmtPart::VLOG_TIME;
} else if (fmt[i] == 'r') {
part.type = FmtPart::TIME;
part.type = FmtPart::VLOG_TIME;
part.realtime = true;
} else {
log_assert(false && "Unexpected character in format substitution");
@ -172,7 +172,7 @@ void Fmt::emit_rtlil(RTLIL::Cell *cell) const {
}
break;
case FmtPart::TIME:
case FmtPart::VLOG_TIME:
log_assert(part.sig.size() == 0);
YS_FALLTHROUGH
case FmtPart::CHARACTER:
@ -205,7 +205,7 @@ void Fmt::emit_rtlil(RTLIL::Cell *cell) const {
fmt += part.signed_ ? 's' : 'u';
} else if (part.type == FmtPart::CHARACTER) {
fmt += 'c';
} else if (part.type == FmtPart::TIME) {
} else if (part.type == FmtPart::VLOG_TIME) {
if (part.realtime)
fmt += 'r';
else
@ -328,7 +328,7 @@ void Fmt::parse_verilog(const std::vector<VerilogFmtArg> &args, bool sformat_lik
case VerilogFmtArg::TIME: {
FmtPart part = {};
part.type = FmtPart::TIME;
part.type = FmtPart::VLOG_TIME;
part.realtime = arg->realtime;
part.padding = ' ';
part.width = 20;
@ -419,7 +419,7 @@ void Fmt::parse_verilog(const std::vector<VerilogFmtArg> &args, bool sformat_lik
part.padding = ' ';
} else if (fmt[i] == 't' || fmt[i] == 'T') {
if (arg->type == VerilogFmtArg::TIME) {
part.type = FmtPart::TIME;
part.type = FmtPart::VLOG_TIME;
part.realtime = arg->realtime;
if (!has_width && !has_leading_zero)
part.width = 20;
@ -541,7 +541,7 @@ std::vector<VerilogFmtArg> Fmt::emit_verilog() const
break;
}
case FmtPart::TIME: {
case FmtPart::VLOG_TIME: {
VerilogFmtArg arg;
arg.type = VerilogFmtArg::TIME;
if (part.realtime)
@ -592,7 +592,7 @@ std::string escape_cxx_string(const std::string &input)
return output;
}
void Fmt::emit_cxxrtl(std::ostream &os, std::string indent, std::function<void(const RTLIL::SigSpec &)> emit_sig) const
void Fmt::emit_cxxrtl(std::ostream &os, std::string indent, std::function<void(const RTLIL::SigSpec &)> emit_sig, const std::string &context) const
{
os << indent << "std::string buf;\n";
for (auto &part : parts) {
@ -602,7 +602,7 @@ void Fmt::emit_cxxrtl(std::ostream &os, std::string indent, std::function<void(c
case FmtPart::STRING: os << "STRING"; break;
case FmtPart::INTEGER: os << "INTEGER"; break;
case FmtPart::CHARACTER: os << "CHARACTER"; break;
case FmtPart::TIME: os << "TIME"; break;
case FmtPart::VLOG_TIME: os << "VLOG_TIME"; break;
}
os << ", ";
os << escape_cxx_string(part.str) << ", ";
@ -620,7 +620,7 @@ void Fmt::emit_cxxrtl(std::ostream &os, std::string indent, std::function<void(c
os << part.realtime;
os << " }.render(";
emit_sig(part.sig);
os << ", itime, ftime);\n";
os << ", " << context << ");\n";
}
os << indent << "return buf;\n";
}
@ -636,8 +636,8 @@ std::string Fmt::render() const
break;
case FmtPart::INTEGER:
case FmtPart::TIME:
case FmtPart::CHARACTER: {
case FmtPart::CHARACTER:
case FmtPart::VLOG_TIME: {
std::string buf;
if (part.type == FmtPart::INTEGER) {
RTLIL::Const value = part.sig.as_const();
@ -720,7 +720,7 @@ std::string Fmt::render() const
} else log_abort();
} else if (part.type == FmtPart::CHARACTER) {
buf = part.sig.as_const().decode_string();
} else if (part.type == FmtPart::TIME) {
} else if (part.type == FmtPart::VLOG_TIME) {
// We only render() during initial, so time is always zero.
buf = "0";
}

8
kernel/fmt.h
View file

@ -56,7 +56,7 @@ struct FmtPart {
STRING = 0,
INTEGER = 1,
CHARACTER = 2,
TIME = 3,
VLOG_TIME = 3,
} type;
// STRING type
@ -65,7 +65,7 @@ struct FmtPart {
// INTEGER/CHARACTER types
RTLIL::SigSpec sig;
// INTEGER/CHARACTER/TIME types
// INTEGER/CHARACTER/VLOG_TIME types
enum {
RIGHT = 0,
LEFT = 1,
@ -78,7 +78,7 @@ struct FmtPart {
bool signed_ = false;
bool plus = false;
// TIME type
// VLOG_TIME type
bool realtime = false;
};
@ -94,7 +94,7 @@ public:
void parse_verilog(const std::vector<VerilogFmtArg> &args, bool sformat_like, int default_base, RTLIL::IdString task_name, RTLIL::IdString module_name);
std::vector<VerilogFmtArg> emit_verilog() const;
void emit_cxxrtl(std::ostream &os, std::string indent, std::function<void(const RTLIL::SigSpec &)> emit_sig) const;
void emit_cxxrtl(std::ostream &os, std::string indent, std::function<void(const RTLIL::SigSpec &)> emit_sig, const std::string &context) const;
std::string render() const;