Marcelina Kościelnicka
7ed9d18907
dfflibmap: Refactor to use dfflegalize internally.
2020-07-09 18:51:03 +02:00
Marcelina Kościelnicka
32d2cc8c28
clkbufmap: improve input pad handling.
...
- allow inserting only the input pad cell
- do not insert the usual buffer if the input pad already acts as a
buffer
2020-07-09 18:48:01 +02:00
Marcelina Kościelnicka
03e28f7ab4
clk2fflogic: Consistently treat async control signals as negative hold.
...
This fixes some dfflegalize equivalence checks, and breaks others — and
I strongly suspect the others are due to bad support for multiple
async inputs in `proc` (in particular, lack of proper support for
dlatchsr and sketchy circuits on dffsr control inputs).
2020-07-09 18:12:47 +02:00
Marcelina Kościelnicka
e9c2c1b717
dfflegalize: Add special support for const-D latches.
...
Those can be created by `opt_dff` when optimizing `$adff` with const
clock, or with D == Q. Make dfflegalize do the opposite transform
when such dlatches would be otherwise unimplementable.
2020-07-09 18:11:32 +02:00
Marcelina Kościelnicka
6b42819a37
dfflegalize: Add tests.
2020-07-01 01:57:15 +02:00
Marcelina Kościelnicka
88e7f90663
Update dff2dffe, dff2dffs, zinit to new FF types.
2020-06-23 18:24:53 +02:00
Eddie Hung
383fe4a4bc
tests: zinit for new types
2020-04-14 13:08:37 -07:00
Marcelina Kościelnicka
7a36728b2f
dffinit: Avoid setting init parameter to zero-length value.
...
Fixes #1704 .
2020-04-14 19:52:19 +02:00
Eddie Hung
b75c5bf743
zinit: resolve one more comment by @mwkmwkmwk
2020-04-13 15:25:37 -07:00
Eddie Hung
c6afce7638
zinit: fix review comments from @mwkmwkmwk
2020-04-13 15:16:51 -07:00
Eddie Hung
091297b9ee
tests: zinit on $adff
2020-04-13 14:29:44 -07:00
Eddie Hung
3c5a9411b1
Add testcase for $_DFF_[NP][NP][01]_
2020-04-13 13:16:49 -07:00
Eddie Hung
d61a6b81fc
Merge pull request #1648 from YosysHQ/eddie/cmp2lcu
...
"techmap -map +/cmp2lcu.v" for decomposing arithmetic compares to $lcu
2020-04-03 16:28:25 -07:00
Eddie Hung
92d70cafec
+/cmp2lcu.v to work efficiently for fully/partially constant inputs
2020-04-03 14:28:22 -07:00
Eddie Hung
f68d723cdc
Refactor +/cmp2lcu.v into recursive techmap
2020-04-03 14:28:22 -07:00
Eddie Hung
9b63700678
techmap +/cmp2lcu.v for decomposing arithmetic compares to $lcu
2020-04-03 14:28:22 -07:00
Marcin Kościelnicki
2d3753d730
iopadmap: Fix z assignment to inout port
...
Fixes #1841 .
2020-04-02 18:15:04 +02:00
Marcin Kościelnicki
c2bf11e42a
techmap: Fix cell names with _TECHMAP_REPLACE_.*
...
Fixes #1804 .
2020-03-23 11:17:07 +01:00
Marcelina Kościelnicka
968956badb
iopadmap: Look harder for already-present buffers. ( #1731 )
...
iopadmap: Look harder for already-present buffers.
Fixes #1720 .
2020-03-02 21:40:09 +01:00
Eddie Hung
3065d4092e
Fine tune #1699 tests
2020-02-13 15:14:58 -08:00
Eddie Hung
ebb11bcea4
iopadmap: move \init attributes from outpad output to its input
2020-02-13 12:05:14 -08:00
Eddie Hung
4c1d3a126d
shiftx2mux: fix select out of bounds
2020-02-05 16:41:09 -08:00
Eddie Hung
b6a1f627b5
Merge remote-tracking branch 'origin/master' into eddie/shiftx2mux
2020-02-05 10:47:31 -08:00
Eddie Hung
8d1b736c4f
Move from +/shiftx2mux.v into +/techmap.v; cleanup
2020-01-21 15:19:41 -08:00
Eddie Hung
7977574995
New techmap +/shiftx2mux.v which decomposes LSB first; better for ABC
2020-01-21 15:19:41 -08:00
Eddie Hung
03ce2c72bb
Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
2020-01-15 16:42:16 -08:00
Eddie Hung
5918ede9bd
abc9: aAdd test to check $_NOT_s are absorbed
2020-01-15 14:36:05 -08:00
Eddie Hung
a6d4ea7463
abc9: respect (* keep *) on cells
2020-01-13 19:21:11 -08:00
Eddie Hung
9ec948f396
write_xaiger: add support and test for (* keep *) on wires
2020-01-13 19:07:55 -08:00
Eddie Hung
a10016ccc5
Add abc9 sanity test
2020-01-09 18:17:06 -08:00
Marcin Kościelnicki
a24596def3
iopadmap: Emit tristate buffers with const OE for some edge cases.
2019-12-25 17:37:58 +01:00
Marcin Kościelnicki
2abe38e73e
iopadmap: Refactor and fix tristate buffer mapping. ( #1527 )
...
The previous code for rerouting wires when inserting tristate buffers
was overcomplicated and didn't handle all cases correctly (in
particular, only cell connections were rewired — internal connections
were not).
2019-12-04 08:44:08 +01:00
Marcin Kościelnicki
6cdea425b8
clkbufmap: Add support for inverters in clock path.
2019-11-25 20:40:39 +01:00
Clifford Wolf
0e05424885
Merge pull request #1422 from YosysHQ/eddie/aigmap_select
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Add -select option to aigmap
2019-10-03 11:54:04 +02:00
Eddie Hung
a4f2f7d23c
Extend test with renaming cells with prefix too
2019-10-02 12:43:18 -07:00
Eddie Hung
369652d4b9
Add test
2019-09-30 17:20:39 -07:00
Eddie Hung
8b239ee707
Add quick test
2019-09-30 15:34:04 -07:00
Marcin Kościelnicki
fd0e3a2c43
Fix _TECHMAP_REMOVEINIT_ handling.
...
Previously, this wire was handled in the code that populated the "do or
do not" techmap cache, resulting in init value removal being performed
only for the first use of a given template.
Fixes the problem identified in #1396 .
2019-09-27 18:34:12 +02:00
Eddie Hung
7c8de1dd18
Hell let's add the original #1381 testcase too
2019-09-20 17:58:51 -07:00
Eddie Hung
6258e6a7e2
Add testcase
2019-09-20 17:51:45 -07:00
Marcin Kościelnicki
c9f9518de4
Added extractinv pass
2019-09-19 04:02:48 +02:00
Marcin Kościelnicki
f72765090c
Add -match-init option to dff2dffs.
2019-09-11 19:38:20 +02:00
Marcin Kościelnicki
a82e8df7d3
techmap: Add support for extracting init values of ports
2019-09-07 16:30:43 +02:00
Marcin Kościelnicki
5fb4b12cb5
improve clkbuf_inhibit propagation upwards through hierarchy
2019-08-27 17:26:47 +02:00
Eddie Hung
528f1c8687
Improve tests to check that clkbuf is connected to expected
2019-08-26 13:45:16 -07:00
Eddie Hung
a0d85393e3
Check clkbuf_inhibit=1 is ignored for custom selection
2019-08-23 11:15:26 -07:00
Eddie Hung
5628e2ec53
Add simple clkbufmap tests
2019-08-23 11:10:02 -07:00
Eddie Hung
d62c10d641
tests/techmap/run-test.sh to cope with *.ys
2019-08-23 11:09:50 -07:00
Eddie Hung
fce8dc7db2
Add test
2019-08-20 20:05:16 -07:00
Clifford Wolf
924d9d6e86
Added read-enable to memory model
2015-09-25 12:23:11 +02:00
