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325 commits

Author SHA1 Message Date
Emil J. Tywoniak
a13b0f6b9e quicklogic: rename dspv1 full synth_quicklogic test for clarity 2025-03-11 10:35:31 +01:00
Emil J. Tywoniak
7380cf6217 quicklogic: ql_dsp_simd add dspv1 test 2025-03-11 10:35:31 +01:00
Emil J. Tywoniak
642c313947 quicklogic: remove irrelevant comments in dspv2 test 2025-03-11 10:35:31 +01:00
Emil J. Tywoniak
9b52ba8738 quicklogic: ql_dsp_simd add dspv2 support, fix dspv1 2025-03-11 10:35:31 +01:00
Emil J. Tywoniak
47b270a03e synth_quicklogic: enable dspv2 tests, fix -dspv2 2025-03-11 10:35:30 +01:00
Emil J. Tywoniak
c451d8ebb9 synth_quicklogic: add -dspv2 to opt into v2 DSP blocks 2025-03-11 10:35:30 +01:00
Martin Povišer
370a033d4e qlf_k6n10f: Start tests 2025-03-11 10:35:01 +01:00
N. Engelhardt
303a386ecc create duplicate IOFFs if multiple output ports are connected to the same register 2025-01-31 11:28:57 +01:00
N. Engelhardt
9da4fe747e fix bus ioff inference 2025-01-28 11:23:36 +01:00
N. Engelhardt
2241a65f78 fix tests not expecting ioffs 2025-01-24 21:29:10 +01:00
N. Engelhardt
1cf8e7c7db add ioff inference for qlf_k6n10f 2025-01-24 21:17:15 +01:00
Emil J. Tywoniak
6240aec433 test: restore verific handling, nicer naming 2024-12-13 10:24:47 +01:00
Emil J. Tywoniak
c26966e3db tests: fix blockrom.v driver conflict 2024-12-02 16:56:42 +01:00
Krystine Sherwin
ee73a91f44
Remove references to ilang 2024-11-05 12:36:31 +13:00
Mohamed Gaber
3d6b8b8e1a
wheels: fix missing yosys-abc/share directory
* `misc/__init__.py`:
  * checks if there's a `yosys-abc` in the same directory - if yes, sets the variable `sys._pyosys_abc`
  * checks if there's a `share` in the same directory - if yes, sets the variable `sys._pyosys_share_dirname`
* `yosys.cc::init_share_dirname`: check for `sys._pyosys_share_dirname`, use it at the highest priority if Python is enabled
* `yosys.cc::init_abc_executable_name`: check for `sys._pyosys_abc`, use it at at the highest priority if Python is enabled
* `Makefile`: add new target, `share`, to only create the extra targets
* `setup.py`: compile libyosys.so, yosys-abc and share, and copy them all as part of the pyosys build
* `test/arch/ecp5/add_sub.py`: ported `add_sub.ys` to Python to act as a test for the share directory and abc with Python wheels, used in CI
2024-10-09 13:09:14 +03:00
Martin Povišer
ca5c2fdff1 quicklogic: Relax the LUT number test 2024-10-07 15:27:03 +02:00
Lofty
13ecbd5c76 quicklogic: test that dividing by a constant does not infer carry chains 2024-10-03 20:05:28 +01:00
Miodrag Milanovic
54d237ff82 add min_ce_use and min_srst_use parameters 2024-08-15 17:50:36 +02:00
Miodrag Milanovic
dbf1d037e8 Cleanup 2024-08-15 17:50:36 +02:00
Miodrag Milanovic
3848563600 Update tests 2024-08-15 17:50:36 +02:00
Miodrag Milanovic
1a6e5c671f Add meminit handling for NX_RFB_U 2024-08-15 17:50:36 +02:00
Miodrag Milanovic
40f05009e3 Fix CY chaining and CI injection 2024-08-15 17:50:36 +02:00
Miodrag Milanovic
f4d8ea4c40 Start adding RFB simulation models 2024-08-15 17:50:36 +02:00
Miodrag Milanovic
7e4aef06e4 Add register file mapping 2024-08-15 17:50:36 +02:00
Miodrag Milanovic
41ae513d60 support other I/O configurations 2024-08-15 17:50:36 +02:00
Miodrag Milanovic
34f08bc639 Enable nanoxplore tests 2024-08-15 17:50:36 +02:00
Miodrag Milanovic
a5bfb23b47 start cleaning rams 2024-08-15 17:50:36 +02:00
Miodrag Milanovic
65d2ebac9d fix test 2024-08-15 17:50:36 +02:00
Lofty
b0c4add642 Added lutram 2024-08-15 17:50:36 +02:00
Lofty
b3f59c9820 Add NX_CY 2024-08-15 17:50:36 +02:00
Lofty
b4e9bb0d85 Add FFs and related tests 2024-08-15 17:50:36 +02:00
Miodrag Milanovic
b4a17cccc3 add few more tests 2024-08-15 17:50:36 +02:00
Miodrag Milanovic
93543bd874 add lut tests 2024-08-15 17:50:36 +02:00
chunlin min
3db69b7a10 inline all tests. Add switch to remove init values as PolarFire DFFs do not support init 2024-07-08 17:03:03 -04:00
Tony Min
d41688f7d7
Revisions (#4)
* area should be 1 for all LUTs

* clean up macros

* add log_assert to fail noisily when encountering oddly configured DFF

* clean help msg

* flatten set to true by default

* update

* merge mult tests

* remove redundant test

* move all dsp tests to single file and remove redundant tests

* update ram tests

* add more dff tests

* fix c++20 compile errors

* add option to dump verilog

* default to use abc9

* remove -abc9 option since its the default now

---------

Co-authored-by: tony <minchunlin@gmail.com>
2024-07-08 10:57:16 -04:00
Tony Min
6fe0e00050
Add missing u sram init (#3)
add missing INIT for uSRAM
2024-07-04 16:39:10 -04:00
chunlin min
8e7ec2d660 add assertions for synth_microchip tests 2024-07-04 15:45:44 -04:00
chunlin min
e3c4791e5b move microchip tests from techlibs/microchip/tests to tests/arch/microchip 2024-07-04 14:16:52 -04:00
Lofty
8cc9aa7fc6 intel_alm: drop quartus support 2024-05-03 11:32:33 +01:00
Miodrag Milanovic
0c7ac36dcf Add workflows and CODEOWNERS and fixed gitignore 2024-04-11 14:56:00 +02:00
Miodrag Milanovic
4ac10040ce Enable SV for localparam use by Efinix cell_sim 2024-04-08 12:45:43 +02:00
Jannis Harder
331ac5285f tests: Run async2sync before sat and/or sim to handle $check cells
Right now neither `sat` nor `sim` have support for the `$check` cell.
For formal verification it is a good idea to always run either
async2sync or clk2fflogic which will (in a future commit) lower `$check`
to `$assert`, etc.

While `sim` should eventually support `$check` directly, using
`async2sync` is ok for the current tests that use `sim`, so this commit
also runs `async2sync` before running sim on designs containing
assertions.
2024-02-01 16:14:11 +01:00
N. Engelhardt
d87bd7ca3f
Merge pull request #3887 from kivikakk/env-bash
tests: use /usr/bin/env for bash.
2023-12-18 16:33:35 +01:00
Martin Povišer
22cc4aff51 quicklogic: Test TDP36K inference with initial data 2023-12-04 15:52:03 +01:00
Krystine Sherwin
e5c32f399a synth_quicklogic: Testing double_sync_ram_tdp 2023-12-04 15:52:03 +01:00
Krystine Sherwin
97354782c0 Adding double_sync_ram_tdp to blockram.v 2023-12-04 15:52:03 +01:00
Krystine Sherwin
215a777eb3 qlf_tests: minor adjustment
Renamed python script so that it sits next to the testbench file when alphabetically sorted.
Reverted `MAX_WIDTH` to full precision for truncation testing.
2023-12-04 15:52:03 +01:00
N. Engelhardt
33ca6994b7 remove example test 2023-12-04 15:52:03 +01:00
N. Engelhardt
3c5b0ab164 fix test setup for synth_quicklogic memory tests 2023-12-04 15:52:03 +01:00
Krystine Sherwin
509d176523 attempting to sim split memory tests
and failing
2023-12-04 15:52:03 +01:00