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Author	SHA1	Message	Date
Emil J. Tywoniak	9f0e4ff03c	satgen: support $connect	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	1e94e0ba6d	rtlil: add dump_sigmap for hacky signorm debugging	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	43944a6e4b	techmap: disable signorm more	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	3833c4eeac	techmap: disable signorm	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	099d9886a7	opt_hier: disable signorm	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	fa890bdb9e	timinginfo: disable output wire check due to signorm	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	a818fcd36b	rtlil: forbid rewrite_sigspecs in signorm	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	c73f1c9fe9	opt_merge_inc: re add initvals deletion	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	3f0e776036	synth_ice40: always read abc9 model to understand port direction	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	da939d86e5	tests: adjust to input_port and init behavior (sketchy)	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	924dba44c7	tests: adjust to input_port and init behavior (sketchy)	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	be64a31a36	tests: adjust to input_port and init behavior (sketchy)	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	e635affe29	wreduce: fixup initvals after setPort	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	90c3aa0a12	ff: fixup initvals with signorm direct drive wire if it's created, not old driven wire	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	1bb29e6a7e	tests: adjust to input_port and init behavior (sketchy)	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	c7ea35e89b	rtlil: fix zero width SigSpec crash in signorm setPort unsetPort	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	b311a7fc73	bug2920: disable	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	81651178b5	rtlil_bufnorm: fix cell deletion deferral bug	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	e8ebac2823	tests: adjust to input_port and init behavior (sketchy)	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	b756c67aba	check: don't fail on $input_port	2026-04-16 15:48:57 +02:00
Emil J. Tywoniak	d46d90ac02	mem: fix signorm cell type morph	2026-04-16 15:48:57 +02:00
Jannis Harder	89589cdbd6	WIP half broken snapshot	2026-04-16 15:48:57 +02:00
Jannis Harder	bc7336499c	WIP remove dead code	2026-04-16 15:48:57 +02:00
nella	413169663d	Merge pull request #5753 from YosysHQ/nella/carry-save-adders ... Add Carry-save adders	2026-04-13 11:16:33 +00:00
nella	4506dffa9f	Fix use after free.	2026-04-13 12:48:05 +02:00
nella	fc71719e6e	Rename csa_tree to arith_tree.	2026-04-13 12:48:05 +02:00
nella	c3c577f333	Fix test cases.	2026-04-13 12:48:05 +02:00
nella	135812ab02	Further CSA cleanup.	2026-04-13 12:48:05 +02:00
nella	847a8941e9	Clang-Format CSA tree.	2026-04-13 12:48:05 +02:00
nella	a02c238874	Consolidate Wallace from booth and CSA.	2026-04-13 12:48:05 +02:00
nella	4bbffecf98	Invert.	2026-04-13 12:48:05 +02:00
nella	42c309347b	Clarify.	2026-04-13 12:48:05 +02:00
Emil J. Tywoniak	b6d656e932	csa_tree: move to techmap	2026-04-13 12:48:05 +02:00
Emil J. Tywoniak	b6a8feec22	csa_tree: refactor	2026-04-13 12:48:05 +02:00
nella	67e145618b	Replace utf arrow with ascii arrow.	2026-04-13 12:48:05 +02:00
nella	4f4c820f73	Cleaned up CSA tests.	2026-04-13 12:48:05 +02:00
nella	9cc2e7d95e	rm misc comments.	2026-04-13 12:48:05 +02:00
nella	0f61ba5299	Move csa after alumacc.	2026-04-13 12:48:05 +02:00
nella	9dc408eea7	CSA add alumacc related tests.	2026-04-13 12:48:05 +02:00
nella	5d90bcc792	CSA add support for macc and alu cells.	2026-04-13 12:48:05 +02:00
nella	fc9adae9a2	Consolidate csa tests.	2026-04-13 12:48:05 +02:00
nella	ab1c423692	Tighten csa tests.	2026-04-13 12:48:05 +02:00
nella	b64b75db7a	Add csa to synth.	2026-04-13 12:48:05 +02:00
nella	cfee6bb4af	Add more robsutness tests.	2026-04-13 12:48:05 +02:00
nella	6b0caedcdd	Add chain tests and tighten synthesis assertions for csa.	2026-04-13 12:48:05 +02:00
nella	335cce4895	Add sub chain support for csa trees.	2026-04-13 12:48:05 +02:00
nella	7183016910	Edge case tests.	2026-04-13 12:48:05 +02:00
nella	1a4a41812c	Add csa synth tests.	2026-04-13 12:48:05 +02:00
nella	4c4c5cf15a	Add structural tests for csa_tree.	2026-04-13 12:48:05 +02:00
nella	e69914b8be	better balancing.	2026-04-13 12:48:05 +02:00