Miodrag Milanovic
f35bdaa527
Update Xilinx cell definitions, fixes #3699
2023-03-23 09:44:36 +01:00
Oliver Keszöcze
fc56978703
Check DREG attribute
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The DSP48E1 implementation checked the wrong attribute (i.e. CREG) to initialize the D input register. This PR fixes 3680
2023-02-17 17:54:41 +01:00
Claire Xenia Wolf
72787f52fc
Fixing old e-mail addresses and deadnames
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s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g ;
2021-06-08 00:39:36 +02:00
Marcelina Kościelnicka
cd6f0732f3
xilinx: Add FDRSE_1, FDCPE_1.
2021-01-27 00:32:00 +01:00
Marcelina Kościelnicka
f2932628fc
xilinx: Add some missing blackbox cells.
2020-12-21 05:34:26 +01:00
Jeff Goeders
8be56960a2
Move signal declarations to before first use
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Signed-off-by: Jeff Goeders <jeff.goeders@gmail.com>
2020-10-19 16:09:18 -06:00
Eddie Hung
de79978372
xilinx: do not make DSP48E1 a whitebox for ABC9 by default ( #2325 )
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* xilinx: eliminate SCCs from DSP48E1 model
* xilinx: add SCC test for DSP48E1
* Update techlibs/xilinx/cells_sim.v
* xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1
Have a test that checks it works through ABC9 when enabled
2020-09-23 09:15:24 -07:00
Keith Rothman
819f1d8c20
Remove EXPLICIT_CARRY logic.
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The symbiflow-arch-defs tool chain no longer needs the EXPLICIT_CARRY
within yosys itself.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2020-07-23 00:56:09 +02:00
Eddie Hung
5b81df57c8
xilinx: tidy up cells_sim.v a little
2020-05-25 09:48:11 -07:00
Eddie Hung
ca4f8c9444
xilinx: gate specify/attributes from iverilog
2020-05-14 10:33:57 -07:00
Eddie Hung
a323881e15
xilinx/ecp5/ice40: add (* abc9_flop *) to bypass-able cells
2020-05-14 10:33:56 -07:00
Eddie Hung
7cd3f4a79b
abc9_ops: add -prep_bypass for auto bypass boxes; refactor
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Eliminate need for abc9_{,un}map.v in xilinx
-prep_dff_{hier,unmap} -> -prep_hier
2020-05-14 10:33:56 -07:00
Eddie Hung
4cec21b93e
abc9_ops: -prep_dff_map to error if async flop found
2020-05-14 10:33:56 -07:00
Eddie Hung
6c66030dfb
Uncomment negative setup times; clamp to zero for connectivity
2020-05-14 10:33:56 -07:00
Eddie Hung
95763c8d18
abc9_ops: add 'dff' label for auto handling of (* abc9_flop *) boxes
2020-05-14 10:33:56 -07:00
Eddie Hung
7b543fdb0c
xilinx: consider DSP48E1.ADREG
2020-03-04 12:04:02 -08:00
Eddie Hung
f65fc845e5
xilinx: improve specify for DSP48E1
2020-03-04 11:31:12 -08:00
Eddie Hung
376319dc8d
xilinx: Update RAMB* specify entries
2020-02-27 10:17:29 -08:00
Eddie Hung
3b74e0fa45
xilinx: add delays to INV
2020-02-27 10:17:29 -08:00
Eddie Hung
b0ffd9cd8b
Make +/xilinx/cells_sim.v legal
2020-02-27 10:17:29 -08:00
Eddie Hung
1ef1ca812b
Get rid of (* abc9_{arrival,required} *) entirely
2020-02-27 10:17:29 -08:00
Eddie Hung
7d86aceee3
Expand +/xilinx/cells_sim.v to keep ICARUS and non -specify paresr happy
2020-02-27 10:17:29 -08:00
Eddie Hung
aac309626b
Fix tests by gating some specify constructs from iverilog
2020-02-27 10:17:29 -08:00
Eddie Hung
e22fee6cdd
abc9_ops: ignore (* abc9_flop *) if not '-dff'
2020-02-27 10:17:29 -08:00
Eddie Hung
8408c13405
Update xilinx for ABC9
2020-02-27 10:17:29 -08:00
Eddie Hung
ccc84f8923
Fix commented out specify statement
2020-02-27 10:17:29 -08:00
Eddie Hung
12d70ca8fb
xilinx: improve specify functionality
2020-02-27 10:17:29 -08:00
Eddie Hung
577545488a
xilinx: use specify blocks in place of abc9_{arrival,required}
2020-02-27 10:17:29 -08:00
Eddie Hung
0e7c55e2a7
Auto-generate .box/.lut files from specify blocks
2020-02-27 10:17:29 -08:00
Eddie Hung
5643c1b8c5
abc9_ops: -prep_lut and -write_lut to auto-generate LUT library
2020-02-27 10:17:29 -08:00
Eddie Hung
0671ae7d79
Merge pull request #1661 from YosysHQ/eddie/abc9_required
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abc9: add support for required times
2020-02-05 18:59:40 +01:00
Marcin Kościelnicki
7e0e42f907
xilinx: Add simulation model for DSP48 (Virtex 4).
2020-01-29 01:40:00 +01:00
Eddie Hung
0e4285ca0d
abc9_ops: generate flop box ids, add abc9_required to FD* cells
2020-01-14 15:05:49 -08:00
Eddie Hung
28f814ee59
Add abc9_required to DSP48E1.{A,B,C,D,PCIN}
2020-01-10 17:12:31 -08:00
Eddie Hung
57f6826e29
Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_required
2020-01-08 18:30:20 -08:00
Eddie Hung
5c89dead5f
Merge branch 'master' of github.com:YosysHQ/yosys
2020-01-06 16:51:32 -08:00
Eddie Hung
01866a7909
Fix DSP48E1 sim
2020-01-06 16:45:29 -08:00
Eddie Hung
98ee8c14df
Merge remote-tracking branch 'origin/master' into xaig_dff
2020-01-06 15:02:44 -08:00
Eddie Hung
28bf712372
Wrap arrival functions inside `YOSYS too
2020-01-06 11:55:56 -08:00
Eddie Hung
27c150bfcc
Fix return value of arrival time functions, fix word
2020-01-06 11:39:08 -08:00
Eddie Hung
020606f81c
Merge remote-tracking branch 'origin/eddie/abc9_refactor' into xaig_arrival_required
2020-01-06 09:44:00 -08:00
Eddie Hung
3012e9eebc
Merge remote-tracking branch 'origin/master' into eddie/abc9_dsp_refactor
2020-01-02 12:48:07 -08:00
Eddie Hung
b454735bea
Merge remote-tracking branch 'origin/master' into xaig_dff
2020-01-02 12:44:06 -08:00
Eddie Hung
d0d3ab8f67
ifndef __ICARUS__ -> ifdef YOSYS
2020-01-01 17:33:47 -08:00
Eddie Hung
3d98a96273
ifdef __ICARUS__ -> ifndef YOSYS
2020-01-01 17:33:10 -08:00
Eddie Hung
db04161eca
Rework abc9's DSP48E1 model
2020-01-01 17:30:26 -08:00
Eddie Hung
44d9fb0e7c
Re-arrange FD order
2019-12-31 18:47:38 -08:00
Eddie Hung
4cdba00e25
FDCE ports to be alphabetical
2019-12-31 15:24:02 -08:00
Eddie Hung
543bd2de6c
Update timings for Xilinx S7 cells
2019-12-30 14:36:07 -08:00
Eddie Hung
405e974fe5
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-30 14:31:42 -08:00
