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11529 commits 98 branches 53 tags 64 MiB
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6 commits

Author SHA1 Message Date
Rupert Swarbrick 1aab608cff Add a test for interfaces on modules loaded on-demand 2021-07-14 22:54:50 -04:00
Clifford Wolf d2aa123226 Fix typo in tests/svinterfaces/runone.sh 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-03 14:40:51 +02:00
Jakob Wenzel 98ffe5fb00 fail svinterfaces testcases on yosys error exit 2019-05-02 09:52:30 +02:00
Clifford Wolf 7d1088afc4 Add missing .gitignore 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-06 07:29:37 +01:00
Ruben Undheim 397dfccb30 Support for SystemVerilog interfaces as a port in the top level module + test case 2018-10-20 11:58:25 +02:00
Ruben Undheim d5aac2650f Basic test for checking correct synthesis of SystemVerilog interfaces 2018-10-18 22:40:53 +02:00