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Author	SHA1	Message	Date
Emil J. Tywoniak	9a89921e67	proc_mux: add comments	2025-11-15 01:58:16 +01:00
Emil J. Tywoniak	c7e2182161	proc_mux: optimize source map locality for index density	2025-11-15 01:04:30 +01:00
Emil J. Tywoniak	8be480895e	proc_dff: add wire src attributes to dff cells	2025-11-07 21:32:09 +01:00
Emil J. Tywoniak	5a797d1678	verific: use SyncActions	2025-11-07 18:23:47 +01:00
Emil J. Tywoniak	26e293d71f	proc_mux: default to case src when action src is missing	2025-11-02 12:42:04 +01:00
Emil J. Tywoniak	0c8e008ce7	proc_mux: add src test	2025-11-02 12:42:04 +01:00
Emil J. Tywoniak	f9c528e981	docs: word_mux grammar	2025-11-02 12:42:04 +01:00
Emil J. Tywoniak	2db4208ca5	proc_mux: refactor	2025-11-02 12:42:04 +01:00
Emil J. Tywoniak	d762c5f5e8	proc_mux: emit fused action location src attributes on procmuxes	2025-11-02 11:26:45 +01:00
Emil J. Tywoniak	304757c881	rtlil: add source tracking to CaseRule actions	2025-11-02 11:25:42 +01:00
Emil J. Tywoniak	c45a035ebf	gowin: lower LUT count sensitivity	2025-11-02 11:22:48 +01:00
Emil J. Tywoniak	b5e5554553	verilog: fix case location	2025-11-02 11:22:33 +01:00
Emil J. Tywoniak	1eb696c786	rtlil: replace SigSig actions with new type SyncAction	2025-11-02 11:22:03 +01:00
github-actions[bot]	37875fdedf	Bump version	2025-10-21 00:23:46 +00:00
Jannis Harder	f6fb423ee8	Merge pull request #5430 from YosysHQ/micko/sim_cycle_width ... sim: Make cycle width small as possible and configurable	2025-10-20 18:51:32 +02:00
Jannis Harder	6a0ee6e4fb	Revert sim's cycle_width default back to 10, but keep -width option	2025-10-20 14:40:05 +02:00
github-actions[bot]	1598771a37	Bump version	2025-10-19 00:26:17 +00:00
Mohamed Gaber	b510c36162	hotfix: headers mistakenly added to clean target ... - fix `make clean` deleting a number of headers when ENABLE_PYOSYS is set to 1	2025-10-18 14:08:20 +01:00
github-actions[bot]	272aa9cde2	Bump version	2025-10-17 00:23:40 +00:00
Maxim Kudinov	6535995005	synth_gowin: fix help hint style	2025-10-16 11:09:28 +01:00
Maxim Kudinov	8c347826f6	synth_gowin: make help description more clear	2025-10-16 11:09:28 +01:00
Maxim Kudinov	8f6d63c082	synth_gowin: make setundef an off by default option	2025-10-16 11:09:28 +01:00
Miodrag Milanovic	f11a61b32b	sim: Make cycle width small as possible and configurable	2025-10-16 11:37:44 +02:00
Miodrag Milanovic	db8c1878a0	fix dlopen using fs:path with mingw	2025-10-16 08:30:43 +02:00
github-actions[bot]	061b6ce2ad	Bump version	2025-10-16 00:23:57 +00:00
Miodrag Milanović	759996b968	Merge pull request #5427 from donn/plugin_search_paths ... plugins: add search paths	2025-10-15 20:02:05 +02:00
Emil J	9d21585a4c	Merge pull request #5426 from rocallahan/parse-sigspec ... Don't stop parsing sigspec after a {} group.	2025-10-15 17:31:11 +02:00
Mohamed Gaber	dce70abd94	plugins: support Windows path delimiters	2025-10-15 15:53:44 +03:00
Mohamed Gaber	e86797f029	plugins: add search path ... This uses the environment variable `YOSYS_PLUGIN_PATH` to provide multiple colon-delimited search paths for native plugins in a similar manner to `PATH` for executables and `PYTHONPATH` for Python modules. This addresses https://github.com/YosysHQ/yosys/issues/2545, allowing Yosys to be better packaged in non-FHS environments such as Nix.	2025-10-15 14:13:25 +03:00
github-actions[bot]	4970ad5a18	Bump version	2025-10-15 00:23:49 +00:00
Robert O'Callahan	e099a7d34a	Don't stop parsing sigspec after a {} group. ... Resolves #5424	2025-10-14 21:18:58 +00:00
Miodrag Milanović	2e3bfca294	Merge pull request #5419 from YosysHQ/micko/verific_fix_nocolumns ... verific: Fix error compiling without VERIFIC_LINEFILE_INCLUDES_COLUMNS	2025-10-14 17:05:31 +02:00
Miodrag Milanović	a89c5b97d8	Merge pull request #5423 from YosysHQ/update_abc ... Update abc	2025-10-14 17:05:13 +02:00
Emil J	a5960ce515	Merge pull request #5197 from YosysHQ/emil/opensta-verilog-export ... OpenSTA verilog compatibility	2025-10-14 16:46:37 +02:00
Miodrag Milanovic	7d2857b30f	Fix regex checks	2025-10-14 16:04:56 +02:00
N. Engelhardt	4513783a02	add tests	2025-10-14 15:48:16 +02:00
Emil J. Tywoniak	e9aedf505c	chtype: replace publish pass with chtype -publish_icells	2025-10-14 15:01:48 +02:00
Miodrag Milanovic	d92cf2f5b0	Compile abc when submodule updates	2025-10-14 14:54:56 +02:00
Miodrag Milanovic	d3d3a9f1ea	Update ABC	2025-10-14 14:47:17 +02:00
Emil J	109abd3224	Merge pull request #5421 from YosysHQ/emil/sort-pass ... sort: init	2025-10-14 10:51:25 +02:00
github-actions[bot]	25f2a88770	Bump version	2025-10-14 00:22:29 +00:00
Emil J. Tywoniak	e5edd2acdb	sort: init	2025-10-13 17:32:26 +02:00
Emil J	71eadc9ab5	Merge pull request #5418 from yrabbit/gw5-dff-and-memory ... Gowin. Reduce the range of flip-flop types.	2025-10-13 17:26:56 +02:00
Emil J. Tywoniak	c46df9ffdc	box_derive: rename -apply to -apply_derived_type	2025-10-13 17:24:32 +02:00
Emil J. Tywoniak	d7cea2c35c	box_derive: add -apply	2025-10-13 17:24:32 +02:00
Emil J. Tywoniak	7d8f92e198	publish: add pass for renaming private cell types to public	2025-10-13 17:24:32 +02:00
Jannis Harder	84b5ec856e	Merge pull request #4320 from YosysHQ/ywb_asserts ... write_btor: Include `$assert` and `$assume` cells in -ywmap output	2025-10-13 15:30:11 +02:00
Miodrag Milanovic	1f11b2c529	verific: Add src to message missed in #5406	2025-10-13 15:16:17 +02:00
Miodrag Milanovic	dc959cdf4a	verific: Fix error compiling without VERIFIC_LINEFILE_INCLUDES_COLUMNS	2025-10-13 15:16:17 +02:00
Miodrag Milanovic	9570b39519	verifix: fix bits() deprecation warnings	2025-10-13 09:57:22 +02:00