Clifford Wolf
|
1eff8be8f0
|
Add support for memory initialization to write_btor
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-03-23 14:40:01 +01:00 |
|
Clifford Wolf
|
e78f5a3055
|
Fix BTOR output tags syntax in writye_btor
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-03-23 14:39:42 +01:00 |
|
Clifford Wolf
|
3b796c033c
|
Add RTLIL::Const::ext[su](), fix RTLIL::SigSpec::extend_u0 for 0-size signals
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-03-23 14:38:48 +01:00 |
|
Clifford Wolf
|
a440f82586
|
Merge pull request #889 from YosysHQ/clifford/fix888
Fix mem2reg handling of memories with upto data ports
|
2019-03-22 18:03:06 +01:00 |
|
Clifford Wolf
|
7d8d0d0155
|
Merge pull request #890 from YosysHQ/clifford/fix887
Trim init attributes when resizing FFs in "wreduce"
|
2019-03-22 18:02:29 +01:00 |
|
David Shah
|
7a6551de36
|
Merge pull request #891 from YosysHQ/xilinx_keep
xilinx: Add keep attribute where appropriate
|
2019-03-22 14:28:29 +00:00 |
|
David Shah
|
46f6a60d58
|
xilinx: Add keep attribute where appropriate
Signed-off-by: David Shah <dave@ds0.me>
|
2019-03-22 13:57:17 +00:00 |
|
Clifford Wolf
|
7cfd83c341
|
Trim init attributes when resizing FFs in "wreduce", fixes #887
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-03-22 11:42:19 +01:00 |
|
Clifford Wolf
|
638be461c3
|
Fix mem2reg handling of memories with upto data ports, fixes #888
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-03-21 22:21:17 +01:00 |
|
Clifford Wolf
|
da42f10765
|
Improve "read_verilog -dump_vlog[12]" handling of upto ranges
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-03-21 22:20:16 +01:00 |
|
Clifford Wolf
|
9b0e7af6d7
|
Improve read_verilog debug output capabilities
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-03-21 20:52:29 +01:00 |
|
Clifford Wolf
|
8c0740bcf7
|
Merge pull request #885 from YosysHQ/clifford/fix873
Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873
|
2019-03-19 20:31:53 +01:00 |
|
Clifford Wolf
|
fe1fb1336b
|
Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-03-19 20:30:28 +01:00 |
|
Eddie Hung
|
a7ac8393d4
|
Merge pull request #808 from eddiehung/read_aiger
Add new read_aiger frontend
|
2019-03-19 09:41:40 -07:00 |
|
Eddie Hung
|
02e8dc7ad2
|
Merge https://github.com/YosysHQ/yosys into read_aiger
|
2019-03-19 08:52:31 -07:00 |
|
Eddie Hung
|
3e89cf68bd
|
Add author name
|
2019-03-19 08:52:06 -07:00 |
|
Clifford Wolf
|
61f37706f9
|
Merge pull request #884 from zachjs/master
fix local name resolution in prefix constructs
|
2019-03-19 14:08:57 +01:00 |
|
Zachary Snow
|
a5f4b83637
|
fix local name resolution in prefix constructs
|
2019-03-18 20:43:20 -04:00 |
|
Clifford Wolf
|
90bce04156
|
Update issue template
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-03-17 12:53:47 +01:00 |
|
Clifford Wolf
|
6aae502a36
|
Update issue template
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-03-17 12:44:23 +01:00 |
|
Clifford Wolf
|
5481205094
|
Merge pull request #877 from FelixVi/master
Add note about test requirements in README
|
2019-03-16 14:19:02 +01:00 |
|
Felix Vietmeyer
|
a71c38f163
|
Add note about test requirements in README
|
2019-03-16 06:20:59 -06:00 |
|
Clifford Wolf
|
aa65d3fe65
|
Improve mix of src/wire/wirebit coverage in "mutate -list"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-03-16 00:55:46 +01:00 |
|
Clifford Wolf
|
3fb363ec8c
|
Merge pull request #876 from YosysHQ/clifford/fmcombine
Add fmcombine pass
|
2019-03-16 00:17:15 +01:00 |
|
Clifford Wolf
|
dacaebae35
|
Add "fmcombine -fwd -bwd -nop"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-03-15 21:45:37 +01:00 |
|
Clifford Wolf
|
370db33a4c
|
Add fmcombine pass
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-03-15 20:46:17 +01:00 |
|
Clifford Wolf
|
b5cf8c9442
|
Merge pull request #875 from YosysHQ/clifford/mutate
Add "mutate" pass
|
2019-03-15 00:51:40 +01:00 |
|
Clifford Wolf
|
9820ed6531
|
Disable realmath tests
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-03-15 00:48:23 +01:00 |
|
Clifford Wolf
|
d1985f6a22
|
Improvements in "mutate" list-reduce algorithm
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-03-15 00:18:31 +01:00 |
|
Clifford Wolf
|
27a5d9c91e
|
Add "mutate -cfg", improve pick_cover behavior
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-03-14 23:20:41 +01:00 |
|
Clifford Wolf
|
4d304e3da7
|
Add a strictly coverage-driven mutation selection strategy
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-03-14 23:01:55 +01:00 |
|
Clifford Wolf
|
2a4263a75d
|
Improve "mutate" wire coverage metric
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-03-14 23:01:01 +01:00 |
|
Clifford Wolf
|
1b4fdbb0d8
|
Add more mutation types, improve mutation src cover
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-03-14 22:04:42 +01:00 |
|
Clifford Wolf
|
bacca57537
|
Fix smtbmc.py handling of zero appended steps
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-03-14 22:04:42 +01:00 |
|
Clifford Wolf
|
6ad5d036c5
|
Add "mutate" command DB reduce functionality
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-03-14 22:04:42 +01:00 |
|
Clifford Wolf
|
76c9c350e7
|
Add hashlib "<container>::element(int n)" methods
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-03-14 22:04:42 +01:00 |
|
Clifford Wolf
|
8e6b69d7bb
|
Add "mutate -mode inv", various other mutate improvements
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-03-14 22:04:42 +01:00 |
|
Clifford Wolf
|
ea8ee24140
|
Add basic "mutate -list N" framework
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-03-14 22:04:42 +01:00 |
|
Clifford Wolf
|
c4575103af
|
Merge pull request #874 from YosysHQ/clifford/andopt
Improve handling of and-with-1 and or-with-0 in opt_expr, fixes #327
|
2019-03-14 21:22:16 +01:00 |
|
Clifford Wolf
|
f806b95ed6
|
Improve handling of and-with-1 and or-with-0 in opt_expr, fixes #327
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-03-14 20:52:00 +01:00 |
|
Clifford Wolf
|
44a44a06ed
|
Merge pull request #872 from YosysHQ/clifford/pmuxfix
Improve handling of "full_case" attributes
|
2019-03-14 18:42:45 +01:00 |
|
Clifford Wolf
|
17caaa3fa8
|
Improve handling of "full_case" attributes
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-03-14 17:51:21 +01:00 |
|
Clifford Wolf
|
04e920337b
|
Fix a syntax bug in ilang backend related to process case statements
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-03-14 17:50:20 +01:00 |
|
Clifford Wolf
|
53b28b3f01
|
Merge pull request #869 from cr1901/win-shell
Install launcher executable when running yosys-smtbmc on Windows.
|
2019-03-14 16:43:23 +01:00 |
|
William D. Jones
|
ff15cf9b1f
|
Install launcher executable when running yosys-smtbmc on Windows.
Signed-off-by: William D. Jones <thor0505@comcast.net>
|
2019-03-13 13:49:16 -04:00 |
|
Clifford Wolf
|
f0b2d8e467
|
Merge pull request #868 from YosysHQ/clifford/fixmem
Various mem2reg-related improvements in handling of memories
|
2019-03-13 13:40:30 +01:00 |
|
Clifford Wolf
|
1cd04a6838
|
Fix a bug in handling quotes in multi-cmd lines in Yosys scripts
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-03-12 21:15:11 +01:00 |
|
Clifford Wolf
|
ac10f72e49
|
Merge pull request #866 from YosysHQ/clifford/idstuff
Improve determinism of IdString DB for similar scripts
|
2019-03-12 20:27:36 +01:00 |
|
Clifford Wolf
|
9284cf92b8
|
Remove ice40/cells_sim.v hack to avoid warning for blocking memory writes
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-03-12 20:14:18 +01:00 |
|
Clifford Wolf
|
d25a0c8ade
|
Improve handling of memories used in mem index expressions on LHS of an assignment
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-03-12 20:12:02 +01:00 |
|