Jannis Harder
96f64f4788
verific: Fix conditions of SVAs with explicit clocks within procedures
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For SVAs that have an explicit clock and are contained in a procedure
which conditionally executes the assertion, verific expresses this using
a mux with one input connected to constant 1 and the other output
connected to an SVA_AT. The existing code only handled the case where
the first input is connected to 1. This patch also handles the other
case.
2022-05-03 14:13:08 +02:00
Miodrag Milanovic
422db937d4
Ignore merging past ffs that we are not properly merging
2022-04-29 14:35:02 +02:00
Miodrag Milanovic
1cc281ca6f
verific: allow memories to be inferred in loops (vhdl)
2022-04-18 09:10:28 +02:00
N. Engelhardt
57bc29c64a
verific: allow memories to be inferred in loops
2022-04-15 15:10:48 +02:00
Miodrag Milanovic
1a1f529099
Preserve internal wires for external nets
2022-04-01 12:07:15 +02:00
Miodrag Milanovic
bbf65702a1
Fix valgrind tests when using verific
2022-03-30 17:25:53 +02:00
Miodrag Milanovic
703769e494
Properly mark modules imported
2022-03-26 09:43:51 +01:00
Miodrag Milanovic
245ecb0529
Import verific netlist in consistent order
2022-03-25 13:44:16 +01:00
Miodrag Milanovic
29293a57bb
Remove quotes if any from attribute
2022-02-16 19:10:13 +01:00
Miodrag Milanovic
2cef48bf2c
Add ability to override verilog mode for verific -f command
2022-02-09 09:19:25 +01:00
Miodrag Milanovic
0b633b6c2e
Use bmux for NTO1MUX
2022-02-02 16:16:08 +01:00
Claire Xenia Wolf
313340aed5
Add YOSYS to the implicitly defined verilog macros in verific
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-12-13 18:20:08 +01:00
Miodrag Milanović
2412497c26
Merge pull request #3102 from YosysHQ/claire/enumxz
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Fix verific import of enum values with x and/or z
2021-12-10 19:36:37 +01:00
Claire Xenia Wolf
2da214d721
Fix verific import of enum values with x and/or z
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-12-10 14:52:27 +01:00
Claire Xen
19773d093f
Update verific.cc
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Ad-hoc fixes/improvements
2021-12-10 14:27:18 +01:00
Miodrag Milanovic
b06f547993
If direction NONE use that from first bit
2021-12-08 11:50:10 +01:00
Miodrag Milanovic
3ebfa3fb84
Make sure cell names are unique for wide operators
2021-12-03 09:49:05 +01:00
Miodrag Milanovic
15a35f5584
No need to alocate more memory than used
2021-11-10 10:50:44 +01:00
Claire Xenia Wolf
2ea757da51
Add "verific -cfg" command
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-11-01 10:41:51 +01:00
Claire Xenia Wolf
83118bfb9e
Fix verific gclk handling for async-load FFs
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-10-31 17:12:29 +01:00
Miodrag Milanovic
f7cc388bb5
Enable async load dff emit by default in Verific
2021-10-27 15:56:56 +02:00
Miodrag Milanovic
32673edfea
Revert "Compile option for enabling async load verific support"
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This reverts commit b8624ad2ae
.
2021-10-27 15:55:43 +02:00
Miodrag Milanovic
b8624ad2ae
Compile option for enabling async load verific support
2021-10-25 09:04:43 +02:00
Claire Xenia Wolf
90b440f870
Fix verific.cc PRIM_DLATCH handling
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-10-21 12:13:35 +02:00
Claire Xenia Wolf
16a177560f
Initial Verific impoter support for {PRIM,WIDE_OPER}_DLATCH{,RS}
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-10-21 05:42:47 +02:00
Miodrag Milanovic
17269ae59b
Option to disable verific VHDL support
2021-10-20 10:02:58 +02:00
Miodrag Milanovic
1aa6896966
Support PRIM_BUFIF1 primitive
2021-10-14 13:04:32 +02:00
Claire Xen
2d3c79458d
Merge pull request #3039 from YosysHQ/claire/verific_aldff
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Add support for $aldff flip-flops to verific importer
2021-10-11 10:01:56 +02:00
Claire Xenia Wolf
c8074769b0
Add Verific adffe/dffsre/aldffe FIXMEs
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-10-11 10:00:20 +02:00
Miodrag Milanovic
93fbc9fba4
Import module attributes from Verific
2021-10-10 10:01:45 +02:00
Claire Xenia Wolf
34f1df8435
Fixes and add comments for open FIXME items
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-10-08 17:24:45 +02:00
Claire Xenia Wolf
1602a03864
Add support for $aldff flip-flops to verific importer
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-10-08 16:21:25 +02:00
Miodrag Milanovic
abc5700628
verific set db_infer_set_reset_registers
2021-10-04 16:48:33 +02:00
Miodrag Milanovic
c3d4bb4cc9
update required verific version
2021-09-02 14:59:16 +02:00
Miodrag Milanovic
b59c427348
Make Verific extensions optional
2021-08-20 10:19:04 +02:00
Miodrag Milanovic
be04d8834e
Require latest verific
2021-08-02 10:29:58 +02:00
Miodrag Milanovic
987fca5297
Update to latest verific
2021-07-21 09:46:53 +02:00
Miodrag Milanovic
7a5ac90985
Update to latest Verific with extensions for initial assertions
2021-07-09 09:02:27 +02:00
Miodrag Milanovic
0dbb05a75e
Add additional help
2021-07-05 09:16:54 +02:00
Miodrag Milanovic
c0d8da20d5
Support command files in Verific
2021-06-16 11:21:44 +02:00
Claire Xenia Wolf
72787f52fc
Fixing old e-mail addresses and deadnames
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s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g ;
2021-06-08 00:39:36 +02:00
Claire Xen
6c56c083f8
Update README
2021-03-04 16:43:30 +01:00
Claire Xen
27d7741540
Merge pull request #2574 from dh73/master
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Accept disable case for SVA liveness properties.
2021-02-15 17:49:11 +01:00
Miodrag Milanovic
13c2fd7137
Ganulate Verific support
2021-02-12 10:08:43 +01:00
Diego H
c96eb2fbd7
Accept disable case for SVA liveness properties.
2021-02-04 15:35:35 -06:00
Miodrag Milanovic
d99c032c27
Require latest Verific build
2021-01-30 09:23:46 +01:00
Claire Xenia Wolf
acad7a6e40
Switch verific bindings from Symbiotic EDA flavored Verific to YosysHQ flavored Verific
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-01-20 20:48:10 +01:00
Miodrag Milanovic
1c4a18f66f
Bump required Verific version
2020-12-02 15:18:04 +01:00
Miodrag Milanovic
c228cb74d6
Update verific version
2020-10-30 08:32:59 +01:00
Miodrag Milanovic
c8f052bbe0
extend verific library API for formal apps and generators
2020-10-12 14:56:15 +02:00