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Author SHA1 Message Date
Clifford Wolf
9522eee02f
Merge pull request #723 from whitequark/synth_ice40_map_gates 
synth_ice40: split `map_gates` off `fine`
 2018-12-16 15:30:08 +01:00
Clifford Wolf
19ca4e2ac3
Merge pull request #722 from whitequark/rename_src 
rename: add -src, for inferring names from source locations
 2018-12-16 15:28:29 +01:00
Clifford Wolf
556341a77f
Merge pull request #720 from whitequark/master 
lut2mux: handle 1-bit INIT constant in $lut cells
 2018-12-16 15:27:23 +01:00
Clifford Wolf
0b9bb852c6 Add yosys-smtbmc support for btor witness 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-10 03:43:07 +01:00
Clifford Wolf
47a5dfdaa4 Add "yosys-smtbmc --btorwit" skeleton 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-08 06:59:27 +01:00
Clifford Wolf
ed3c57fad3 Fix btor init value handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-08 06:21:31 +01:00
David Shah
435776120a
Merge pull request #727 from whitequark/opt_lut 
opt_lut: leave intact LUTs with cascade feeding module outputs
 2018-12-07 17:17:26 +00:00
whitequark
7ec740b7ad opt_lut: leave intact LUTs with cascade feeding module outputs. 2018-12-07 17:13:52 +00:00
whitequark
9eb03d458d opt_lut: show original truth table for both cells. 2018-12-07 17:04:41 +00:00
whitequark
a8ab722824 opt_lut: add -limit option, for debugging misoptimizations. 2018-12-07 16:36:26 +00:00
whitequark
6e559ee3c7 synth_ice40: split map_gates off fine. 2018-12-06 12:04:39 +00:00
Clifford Wolf
7d1088afc4 Add missing .gitignore 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-06 07:29:37 +01:00
Clifford Wolf
643f858acf Bugfix in opt_expr handling of a<0 and a>=0 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-06 07:29:21 +01:00
Clifford Wolf
910d94b212 Verific updates 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-06 07:21:50 +01:00
whitequark
a9baee4b24 rename: add -src, for inferring names from source locations. 2018-12-05 20:35:13 +00:00
whitequark
d1f2cb01dc lut2mux: handle 1-bit INIT constant in $lut cells. 
This pass already handles INIT constants shorter than 2^width, but
that was not done for the recursion base case.
 2018-12-05 19:27:48 +00:00
whitequark
88217d0157 opt_lut: simplify type conversion. NFC. 2018-12-05 19:12:02 +00:00
Clifford Wolf
1bb728e24f
Merge pull request #709 from smunaut/issue_708 
Make return value of $clog2 signed
 2018-12-05 09:19:44 -08:00
Clifford Wolf
728a251a95
Merge pull request #718 from whitequark/gate2lut 
gate2lut: new techlib, for converting Yosys gates to FPGA LUTs
 2018-12-05 09:16:35 -08:00
whitequark
d9fa4387c9 synth_ice40: add -noabc option, to use built-in LUT techmapping. 
This should be combined with -relut to get sensible results.
 2018-12-05 17:13:46 +00:00
whitequark
9ef078848a gate2lut: new techlib, for converting Yosys gates to FPGA LUTs. 2018-12-05 17:13:27 +00:00
whitequark
12596b5003 Fix typo. 2018-12-05 17:13:27 +00:00
Clifford Wolf
e115303129
Merge pull request #713 from Diego-HR/master 
Changes in GoWin synth commands and ALU primitive support
 2018-12-05 09:08:30 -08:00
Clifford Wolf
1a260ce89b
Merge pull request #712 from mmicko/anlogic-support 
Initial support for Anlogic FPGA
 2018-12-05 09:08:04 -08:00
Clifford Wolf
2d98db73e3 Rename opt_lut.cpp to opt_lut.cc 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-05 18:03:58 +01:00
Clifford Wolf
50a94ce4fc
Merge pull request #717 from whitequark/opt_lut 
Add a new opt_lut pass, which combines inefficiently packed LUTs
 2018-12-05 09:02:13 -08:00
Clifford Wolf
11323665af
Merge pull request #716 from whitequark/ice40_unlut 
Extract ice40_unlut pass from ice40_opt
 2018-12-05 08:59:21 -08:00
whitequark
45cb6200af opt_lut: add -dlogic, to avoid disturbing logic such as carry chains. 2018-12-05 16:30:37 +00:00
whitequark
e603484070 opt_lut: always prefer to eliminate 1-LUTs. 
These are always either buffers or inverters, and keeping the larger
LUT preserves more source-level information about the design.
 2018-12-05 16:30:37 +00:00
whitequark
59eea0183f opt_lut: collect and display statistics. 2018-12-05 16:30:37 +00:00
whitequark
e54c7e951c opt_lut: refactor to use a worker. NFC. 2018-12-05 16:30:37 +00:00
whitequark
ea4870b126 synth_ice40: add -relut option, to run ice40_unlut and opt_lut. 2018-12-05 16:30:37 +00:00
whitequark
9e072ec21f opt_lut: new pass, to combine LUTs for tighter packing. 2018-12-05 16:30:37 +00:00
whitequark
1719aa88ac Extract ice40_unlut pass from ice40_opt. 
Currently, `ice40_opt -unlut` would map SB_LUT4 to $lut and convert
them back to logic immediately. This is not desirable if the goal
is to operate on $lut cells. If this is desirable, the same result
as `ice40_opt -unlut` can be achieved by running simplemap and opt
after ice40_unlut.
 2018-12-05 16:30:24 +00:00
Serge Bazanski
615b30bd29
Merge pull request #719 from YosysHQ/q3k/flailing-around-trying-to-fix-osx 
Fix Travis on OSX
 2018-12-05 17:22:14 +01:00
Sergiusz Bazanski
323480d66b travis/osx: fix, use clang instead of gcc 2018-12-05 15:54:08 +01:00
Clifford Wolf
c800e3bb16 Fix typo 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-04 23:30:23 +01:00
Clifford Wolf
70c417174d
Merge pull request #702 from smunaut/min_ce_use 
Add option to only use DFFE is the resulting E signal would be use > N times
 2018-12-04 14:29:21 -08:00
Diego H
819ca73096 Changes in GoWin synth commands and ALU primitive support 2018-12-03 20:08:35 -06:00
Miodrag Milanovic
43030db5ff Leave only real black box cells 2018-12-02 11:57:50 +01:00
Miodrag Milanovic
83bce9f59c Initial support for Anlogic FPGA 2018-12-01 18:28:54 +01:00
Clifford Wolf
47c89d600c
Merge pull request #676 from rafaeltp/master 
Splits SigSpec into bits before calling check_signal_in_fanout (solves #675)
 2018-12-01 04:11:19 +01:00
Clifford Wolf
e90195b737 Improve ConstEval error handling for non-eval cell types 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-29 05:07:40 +01:00
Sylvain Munaut
3e5ab50a73 ice40: Add option to only use CE if it'd be use by more than X FFs 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-27 21:50:42 +01:00
Sylvain Munaut
8d3ab626ea dff2dffe: Add option for unmap to only remove DFFE with low CE signal use 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-27 21:50:42 +01:00
Sylvain Munaut
86ce43999e Make return value of $clog2 signed 
As per Verilog 2005 - 17.11.1.

Fixes #708

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-24 18:49:23 +01:00
Clifford Wolf
ab97eddee9 Add iteration limit to "opt_muxtree" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-20 17:56:47 +01:00
Clifford Wolf
9228f015a3 Update ABC to git rev 2ddc57d 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-13 17:22:28 +01:00
Clifford Wolf
82aaf6d908 Add "write_aiger -I -O -B" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-12 09:27:33 +01:00
Clifford Wolf
ef1c61aae4 Merge branch 'master' of github.com:YosysHQ/yosys 2018-11-12 09:10:25 +01:00