Krystine Sherwin
2d6738bb10
qlf_tests: minor adjustment
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Renamed python script so that it sits next to the testbench file when alphabetically sorted.
Reverted `MAX_WIDTH` to full precision for truncation testing.
2023-12-04 09:38:48 +13:00
N. Engelhardt
1bd3678f75
remove example test
2023-12-01 14:28:50 +01:00
N. Engelhardt
c2fc33f0eb
fix test setup for synth_quicklogic memory tests
2023-12-01 14:03:07 +01:00
N. Engelhardt
190cbd54b1
fix test setup for synth_quicklogic memory tests
2023-12-01 10:47:39 +01:00
Krystine Sherwin
5634d98ccb
attempting to sim split memory tests
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and failing
2023-12-01 21:16:58 +13:00
Krystine Sherwin
d9d54e66c7
QLF_TDP36K: asymmetric simulation tests
2023-12-01 20:47:39 +13:00
Krystine Sherwin
0cd4a10c81
QLF_TDP36K: truncation tests matter
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Expected values are now stored in full precision rather than truncating to the same value as the input.
i.e. 0x5a5a5a5a will truncate to 0x5a5a for write data but will remain 0x5a5a5a5a for expected read.
2023-12-01 17:14:01 +13:00
Krystine Sherwin
7f90fafd15
QLF_TDP36K: more basic tdp/sdp sim tests
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Adds TDP submodule to generator.
Adds shorthand expected signal to testbench (mostly to make it easier when I look at the vcd dump to figure out what I did wrong in tests).
2023-12-01 17:00:15 +13:00
Krystine Sherwin
7a659bdd26
QLF_TDP36K: parameterised sim test gen
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Also limited to 16 tests per file to allow parallelism.
Previous tests are converted to new test format with no sim test steps.
2023-12-01 16:26:00 +13:00
Krystine Sherwin
b62173775c
QLF_TDP36K: test bram_tdp post synth
2023-12-01 09:52:27 +13:00
N. Engelhardt
64609afe2c
add example memory test
2023-11-30 19:35:43 +01:00
Krystine Sherwin
f810bd88f5
quicklogic: wildcard asymmetric memory tests
2023-11-30 17:33:13 +01:00
Krystine Sherwin
cdb20baf1f
quicklogic: testing port widths on split rams
2023-11-30 17:33:13 +01:00
Krystine Sherwin
4c03c84fa7
quicklogic: testing 1:4 assymetric memory
2023-11-30 17:33:13 +01:00
Krystine Sherwin
a1073c706e
quicklogic: fix double width read
2023-11-30 17:33:13 +01:00
Krystine Sherwin
fbf8607b97
quicklogic: Testing split TDP36K
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Adds `double_sync_ram_sdp` to `common/blockram.v`, providing a test for two disjoint memories.
Refactor python blockram template to take a list of params to support the above.
Also change the smaller single TDP36K tests to also test `port_a_width` value.
2023-11-30 17:33:13 +01:00
Krystine Sherwin
0cd67ce473
quicklogic: Initial blockram tests
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Use python script to generate tests for both SDP and TDP across multiple sizes of RAM.
Adds sync_ram_sdp_(wwr|wrr) to common blockram.v for double width write and double width read respectively.
2023-11-30 17:33:13 +01:00
Martin Povišer
fb34167fd4
fixup! quicklogic: Add basic k6n10f tests
2023-11-30 13:43:56 +01:00
Martin Povišer
d11a85fcba
fixup! quicklogic: Add basic k6n10f tests
2023-11-30 11:12:55 +01:00
Martin Povišer
193144e68b
fixup! quicklogic: Add basic k6n10f tests
2023-11-30 10:45:39 +01:00
Martin Povišer
e70122b74e
fixup! quicklogic: Add basic k6n10f tests
2023-11-29 11:20:16 +01:00
Martin Povišer
5bc587c843
quicklogic: Add k6n10f DSP test
2023-11-27 17:43:21 +01:00
Martin Povišer
502559cba4
quicklogic: Fix dffs.ys test
2023-11-27 17:27:46 +01:00
Martin Povišer
a3b3333eeb
quicklogic: Add basic k6n10f tests
2023-11-27 12:14:48 +01:00
Martin Povišer
74296e3d92
quicklogic: Move pp3 tests one level down
2023-11-27 12:05:55 +01:00
N. Engelhardt
e230a871be
synth_quicklogic: rearrange files to prepare for adding more architectures
2023-11-27 08:37:33 +01:00
Martin Povišer
62d6338688
quicklogic: Fix pp3 dffs test
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Fix name confusion which was making the test look into the vendor's cell
blackbox rather than into the synthesis results.
2023-10-12 12:45:40 +02:00
Lofty
dce037a62c
quicklogic: ABC9 synthesis
2021-04-17 20:54:58 +02:00
Marcelina Kościelnicka
4a35f244aa
quicklogic: Add .gitignore file for test outputs.
2021-03-23 17:35:00 +01:00
Lofty
f4298b057a
quicklogic: PolarPro 3 support
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Co-authored-by: Grzegorz Latosiński <glatosinski@antmicro.com>
Co-authored-by: Maciej Kurc <mkurc@antmicro.com>
Co-authored-by: Tarachand Pagarani <tpagarani@quicklogic.com>
Co-authored-by: Lalit Sharma <lsharma@quicklogic.com>
Co-authored-by: kkumar23 <kkumar@quicklogic.com>
2021-03-18 13:28:16 +01:00
